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@@ -15,6 +15,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/i2c-gpio.h>
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+#include <linux/atmel-mci.h>
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#include <linux/fb.h>
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#include <video/atmel_lcdc.h>
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@@ -25,6 +26,7 @@
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#include <mach/at91sam9g45_matrix.h>
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#include <mach/at91sam9_smc.h>
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#include <mach/at_hdmac.h>
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+#include <mach/atmel-mci.h>
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#include "generic.h"
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@@ -349,6 +351,169 @@ void __init at91_add_device_eth(struct at91_eth_data *data) {}
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#endif
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+/* --------------------------------------------------------------------
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+ * MMC / SD
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+ * -------------------------------------------------------------------- */
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+
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+#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
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+static u64 mmc_dmamask = DMA_BIT_MASK(32);
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+static struct mci_platform_data mmc0_data, mmc1_data;
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+
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+static struct resource mmc0_resources[] = {
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+ [0] = {
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+ .start = AT91SAM9G45_BASE_MCI0,
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+ .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = AT91SAM9G45_ID_MCI0,
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+ .end = AT91SAM9G45_ID_MCI0,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct platform_device at91sam9g45_mmc0_device = {
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+ .name = "atmel_mci",
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+ .id = 0,
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+ .dev = {
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+ .dma_mask = &mmc_dmamask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ .platform_data = &mmc0_data,
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+ },
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+ .resource = mmc0_resources,
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+ .num_resources = ARRAY_SIZE(mmc0_resources),
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+};
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+
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+static struct resource mmc1_resources[] = {
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+ [0] = {
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+ .start = AT91SAM9G45_BASE_MCI1,
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+ .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = AT91SAM9G45_ID_MCI1,
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+ .end = AT91SAM9G45_ID_MCI1,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct platform_device at91sam9g45_mmc1_device = {
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+ .name = "atmel_mci",
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+ .id = 1,
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+ .dev = {
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+ .dma_mask = &mmc_dmamask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ .platform_data = &mmc1_data,
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+ },
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+ .resource = mmc1_resources,
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+ .num_resources = ARRAY_SIZE(mmc1_resources),
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+};
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+
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+/* Consider only one slot : slot 0 */
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+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
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+{
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+
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+ if (!data)
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+ return;
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+
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+ /* Must have at least one usable slot */
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+ if (!data->slot[0].bus_width)
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+ return;
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+
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+#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
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+ {
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+ struct at_dma_slave *atslave;
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+ struct mci_dma_data *alt_atslave;
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+
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+ alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
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+ atslave = &alt_atslave->sdata;
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+
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+ /* DMA slave channel configuration */
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+ atslave->dma_dev = &at_hdmac_device.dev;
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+ atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
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+ atslave->cfg = ATC_FIFOCFG_HALFFIFO
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+ | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
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+ atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
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+ if (mmc_id == 0) /* MCI0 */
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+ atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
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+ | ATC_DST_PER(AT_DMA_ID_MCI0);
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+
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+ else /* MCI1 */
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+ atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
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+ | ATC_DST_PER(AT_DMA_ID_MCI1);
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+
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+ data->dma_slave = alt_atslave;
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+ }
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+#endif
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+
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+
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+ /* input/irq */
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+ if (data->slot[0].detect_pin) {
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+ at91_set_gpio_input(data->slot[0].detect_pin, 1);
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+ at91_set_deglitch(data->slot[0].detect_pin, 1);
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+ }
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+ if (data->slot[0].wp_pin)
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+ at91_set_gpio_input(data->slot[0].wp_pin, 1);
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+
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+ if (mmc_id == 0) { /* MCI0 */
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+
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+ /* CLK */
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+ at91_set_A_periph(AT91_PIN_PA0, 0);
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+
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+ /* CMD */
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+ at91_set_A_periph(AT91_PIN_PA1, 1);
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+
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+ /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
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+ at91_set_A_periph(AT91_PIN_PA2, 1);
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+ if (data->slot[0].bus_width == 4) {
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+ at91_set_A_periph(AT91_PIN_PA3, 1);
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+ at91_set_A_periph(AT91_PIN_PA4, 1);
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+ at91_set_A_periph(AT91_PIN_PA5, 1);
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+ if (data->slot[0].bus_width == 8) {
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+ at91_set_A_periph(AT91_PIN_PA6, 1);
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+ at91_set_A_periph(AT91_PIN_PA7, 1);
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+ at91_set_A_periph(AT91_PIN_PA8, 1);
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+ at91_set_A_periph(AT91_PIN_PA9, 1);
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+ }
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+ }
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+
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+ mmc0_data = *data;
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+ at91_clock_associate("mci0_clk", &at91sam9g45_mmc0_device.dev, "mci_clk");
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+ platform_device_register(&at91sam9g45_mmc0_device);
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+
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+ } else { /* MCI1 */
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+
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+ /* CLK */
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+ at91_set_A_periph(AT91_PIN_PA31, 0);
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+
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+ /* CMD */
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+ at91_set_A_periph(AT91_PIN_PA22, 1);
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+
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+ /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
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+ at91_set_A_periph(AT91_PIN_PA23, 1);
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+ if (data->slot[0].bus_width == 4) {
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+ at91_set_A_periph(AT91_PIN_PA24, 1);
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+ at91_set_A_periph(AT91_PIN_PA25, 1);
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+ at91_set_A_periph(AT91_PIN_PA26, 1);
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+ if (data->slot[0].bus_width == 8) {
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+ at91_set_A_periph(AT91_PIN_PA27, 1);
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+ at91_set_A_periph(AT91_PIN_PA28, 1);
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+ at91_set_A_periph(AT91_PIN_PA29, 1);
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+ at91_set_A_periph(AT91_PIN_PA30, 1);
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+ }
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+ }
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+
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+ mmc1_data = *data;
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+ at91_clock_associate("mci1_clk", &at91sam9g45_mmc1_device.dev, "mci_clk");
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+ platform_device_register(&at91sam9g45_mmc1_device);
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+
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+ }
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+}
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+#else
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+void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
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+#endif
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+
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+
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/* --------------------------------------------------------------------
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* NAND / SmartMedia
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* -------------------------------------------------------------------- */
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