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@@ -51,7 +51,6 @@ union gic_base {
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};
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struct gic_chip_data {
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- unsigned int irq_offset;
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union gic_base dist_base;
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union gic_base cpu_base;
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#ifdef CONFIG_CPU_PM
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@@ -61,9 +60,7 @@ struct gic_chip_data {
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u32 __percpu *saved_ppi_enable;
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u32 __percpu *saved_ppi_conf;
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#endif
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-#ifdef CONFIG_IRQ_DOMAIN
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- struct irq_domain domain;
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-#endif
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+ struct irq_domain *domain;
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unsigned int gic_irqs;
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#ifdef CONFIG_GIC_NON_BANKED
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void __iomem *(*get_base)(union gic_base *);
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@@ -282,7 +279,7 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
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irqnr = irqstat & ~0x1c00;
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if (likely(irqnr > 15 && irqnr < 1021)) {
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- irqnr = irq_domain_to_irq(&gic->domain, irqnr);
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+ irqnr = irq_find_mapping(gic->domain, irqnr);
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handle_IRQ(irqnr, regs);
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continue;
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}
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@@ -314,8 +311,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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if (gic_irq == 1023)
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goto out;
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- cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);
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- if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
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+ cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
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+ if (unlikely(gic_irq < 32 || gic_irq > 1020))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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@@ -348,10 +345,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
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static void __init gic_dist_init(struct gic_chip_data *gic)
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{
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- unsigned int i, irq;
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+ unsigned int i;
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u32 cpumask;
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unsigned int gic_irqs = gic->gic_irqs;
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- struct irq_domain *domain = &gic->domain;
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void __iomem *base = gic_data_dist_base(gic);
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u32 cpu = cpu_logical_map(smp_processor_id());
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@@ -386,23 +382,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
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for (i = 32; i < gic_irqs; i += 32)
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writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
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- /*
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- * Setup the Linux IRQ subsystem.
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- */
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- irq_domain_for_each_irq(domain, i, irq) {
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- if (i < 32) {
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- irq_set_percpu_devid(irq);
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- irq_set_chip_and_handler(irq, &gic_chip,
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- handle_percpu_devid_irq);
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- set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
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- } else {
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- irq_set_chip_and_handler(irq, &gic_chip,
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- handle_fasteoi_irq);
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- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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- }
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- irq_set_chip_data(irq, gic);
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- }
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-
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writel_relaxed(1, base + GIC_DIST_CTRL);
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}
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@@ -618,7 +597,23 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
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}
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#endif
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-#ifdef CONFIG_OF
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+static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hw)
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+{
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+ if (hw < 32) {
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+ irq_set_percpu_devid(irq);
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+ irq_set_chip_and_handler(irq, &gic_chip,
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+ handle_percpu_devid_irq);
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+ set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
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+ } else {
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+ irq_set_chip_and_handler(irq, &gic_chip,
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+ handle_fasteoi_irq);
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+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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+ }
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+ irq_set_chip_data(irq, d->host_data);
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+ return 0;
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+}
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+
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static int gic_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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@@ -639,26 +634,23 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
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*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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-#endif
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struct irq_domain_ops gic_irq_domain_ops = {
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-#ifdef CONFIG_OF
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+ .map = gic_irq_domain_map,
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.xlate = gic_irq_domain_xlate,
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-#endif
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};
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void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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void __iomem *dist_base, void __iomem *cpu_base,
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- u32 percpu_offset)
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+ u32 percpu_offset, struct device_node *node)
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{
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+ irq_hw_number_t hwirq_base;
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struct gic_chip_data *gic;
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- struct irq_domain *domain;
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- int gic_irqs;
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+ int gic_irqs, irq_base;
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BUG_ON(gic_nr >= MAX_GIC_NR);
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gic = &gic_data[gic_nr];
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- domain = &gic->domain;
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#ifdef CONFIG_GIC_NON_BANKED
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if (percpu_offset) { /* Frankein-GIC without banked registers... */
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unsigned int cpu;
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@@ -694,10 +686,10 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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* For primary GICs, skip over SGIs.
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* For secondary GICs, skip over PPIs, too.
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*/
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- domain->hwirq_base = 32;
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+ hwirq_base = 32;
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if (gic_nr == 0) {
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if ((irq_start & 31) > 0) {
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- domain->hwirq_base = 16;
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+ hwirq_base = 16;
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if (irq_start != -1)
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irq_start = (irq_start & ~31) + 16;
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}
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@@ -713,17 +705,17 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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gic_irqs = 1020;
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gic->gic_irqs = gic_irqs;
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- domain->nr_irq = gic_irqs - domain->hwirq_base;
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- domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq,
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- numa_node_id());
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- if (IS_ERR_VALUE(domain->irq_base)) {
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+ gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
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+ irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
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+ if (IS_ERR_VALUE(irq_base)) {
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WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
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irq_start);
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- domain->irq_base = irq_start;
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+ irq_base = irq_start;
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}
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- domain->host_data = gic;
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- domain->ops = &gic_irq_domain_ops;
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- irq_domain_add(domain);
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+ gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
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+ hwirq_base, &gic_irq_domain_ops, gic);
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+ if (WARN_ON(!gic->domain))
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+ return;
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gic_chip.flags |= gic_arch_extn.flags;
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gic_dist_init(gic);
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@@ -768,7 +760,6 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
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void __iomem *dist_base;
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u32 percpu_offset;
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int irq;
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- struct irq_domain *domain = &gic_data[gic_cnt].domain;
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if (WARN_ON(!node))
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return -ENODEV;
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@@ -782,9 +773,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
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if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
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percpu_offset = 0;
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- domain->of_node = of_node_get(node);
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-
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- gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
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+ gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
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if (parent) {
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irq = irq_of_parse_and_map(node, 0);
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