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@@ -180,6 +180,53 @@
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#define DA8XX_LPSC1_CR_P3_SS 26
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#define DA8XX_LPSC1_L3_CBA_RAM 31
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+/* TNETV107X LPSC Assignments */
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+#define TNETV107X_LPSC_ARM 0
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+#define TNETV107X_LPSC_GEM 1
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+#define TNETV107X_LPSC_DDR2_PHY 2
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+#define TNETV107X_LPSC_TPCC 3
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+#define TNETV107X_LPSC_TPTC0 4
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+#define TNETV107X_LPSC_TPTC1 5
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+#define TNETV107X_LPSC_RAM 6
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+#define TNETV107X_LPSC_MBX_LITE 7
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+#define TNETV107X_LPSC_LCD 8
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+#define TNETV107X_LPSC_ETHSS 9
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+#define TNETV107X_LPSC_AEMIF 10
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+#define TNETV107X_LPSC_CHIP_CFG 11
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+#define TNETV107X_LPSC_TSC 12
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+#define TNETV107X_LPSC_ROM 13
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+#define TNETV107X_LPSC_UART2 14
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+#define TNETV107X_LPSC_PKTSEC 15
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+#define TNETV107X_LPSC_SECCTL 16
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+#define TNETV107X_LPSC_KEYMGR 17
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+#define TNETV107X_LPSC_KEYPAD 18
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+#define TNETV107X_LPSC_GPIO 19
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+#define TNETV107X_LPSC_MDIO 20
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+#define TNETV107X_LPSC_SDIO0 21
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+#define TNETV107X_LPSC_UART0 22
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+#define TNETV107X_LPSC_UART1 23
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+#define TNETV107X_LPSC_TIMER0 24
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+#define TNETV107X_LPSC_TIMER1 25
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+#define TNETV107X_LPSC_WDT_ARM 26
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+#define TNETV107X_LPSC_WDT_DSP 27
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+#define TNETV107X_LPSC_SSP 28
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+#define TNETV107X_LPSC_TDM0 29
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+#define TNETV107X_LPSC_VLYNQ 30
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+#define TNETV107X_LPSC_MCDMA 31
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+#define TNETV107X_LPSC_USB0 32
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+#define TNETV107X_LPSC_TDM1 33
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+#define TNETV107X_LPSC_DEBUGSS 34
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+#define TNETV107X_LPSC_ETHSS_RGMII 35
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+#define TNETV107X_LPSC_SYSTEM 36
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+#define TNETV107X_LPSC_IMCOP 37
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+#define TNETV107X_LPSC_SPARE 38
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+#define TNETV107X_LPSC_SDIO1 39
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+#define TNETV107X_LPSC_USB1 40
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+#define TNETV107X_LPSC_USBSS 41
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+#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
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+#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
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+#define TNETV107X_LPSC_MAX 44
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+
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/* PSC register offsets */
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#define EPCPR 0x070
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#define PTCMD 0x120
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