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@@ -46,19 +46,27 @@
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void rs600_gpu_init(struct radeon_device *rdev);
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int rs600_mc_wait_for_idle(struct radeon_device *rdev);
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+static const u32 crtc_offsets[2] =
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+{
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+ 0,
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+ AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
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+};
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+
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void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
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{
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- struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
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int i;
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- if (RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset) & AVIVO_CRTC_EN) {
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+ if (crtc >= rdev->num_crtc)
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+ return;
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+
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+ if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) {
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for (i = 0; i < rdev->usec_timeout; i++) {
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- if (!(RREG32(AVIVO_D1CRTC_STATUS + radeon_crtc->crtc_offset) & AVIVO_D1CRTC_V_BLANK))
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+ if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK))
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break;
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udelay(1);
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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- if (RREG32(AVIVO_D1CRTC_STATUS + radeon_crtc->crtc_offset) & AVIVO_D1CRTC_V_BLANK)
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+ if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
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break;
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udelay(1);
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}
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