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@@ -356,6 +356,29 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
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uint32_t aux_clock_divider;
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int try, precharge;
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+ if (IS_HASWELL(dev)) {
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+ switch (intel_dp->port) {
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+ case PORT_A:
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+ ch_ctl = DPA_AUX_CH_CTL;
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+ ch_data = DPA_AUX_CH_DATA1;
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+ break;
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+ case PORT_B:
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+ ch_ctl = PCH_DPB_AUX_CH_CTL;
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+ ch_data = PCH_DPB_AUX_CH_DATA1;
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+ break;
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+ case PORT_C:
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+ ch_ctl = PCH_DPC_AUX_CH_CTL;
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+ ch_data = PCH_DPC_AUX_CH_DATA1;
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+ break;
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+ case PORT_D:
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+ ch_ctl = PCH_DPD_AUX_CH_CTL;
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+ ch_data = PCH_DPD_AUX_CH_DATA1;
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+ break;
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+ default:
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+ BUG();
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+ }
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+ }
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+
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intel_dp_check_edp(intel_dp);
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/* The clock divider is based off the hrawclk,
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* and would like to run at 2MHz. So, take the
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