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@@ -38,13 +38,15 @@
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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-#include <linux/pinctrl/consumer.h>
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+#include <linux/gcd.h>
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#include <linux/spi/spi.h>
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#include <linux/platform_data/spi-omap2-mcspi.h>
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#define OMAP2_MCSPI_MAX_FREQ 48000000
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+#define OMAP2_MCSPI_MAX_FIFODEPTH 64
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+#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
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#define SPI_AUTOSUSPEND_TIMEOUT 2000
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#define OMAP2_MCSPI_REVISION 0x00
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@@ -54,6 +56,7 @@
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#define OMAP2_MCSPI_WAKEUPENABLE 0x20
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#define OMAP2_MCSPI_SYST 0x24
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#define OMAP2_MCSPI_MODULCTRL 0x28
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+#define OMAP2_MCSPI_XFERLEVEL 0x7c
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/* per-channel banks, 0x14 bytes each, first is: */
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#define OMAP2_MCSPI_CHCONF0 0x2c
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@@ -63,6 +66,7 @@
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#define OMAP2_MCSPI_RX0 0x3c
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/* per-register bitmasks: */
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+#define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
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#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
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#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
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@@ -83,10 +87,13 @@
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#define OMAP2_MCSPI_CHCONF_IS BIT(18)
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#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
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#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
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+#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
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+#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
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#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
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#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
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#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
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+#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
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#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
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@@ -102,6 +109,9 @@ struct omap2_mcspi_dma {
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struct completion dma_tx_completion;
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struct completion dma_rx_completion;
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+
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+ char dma_rx_ch_name[14];
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+ char dma_tx_ch_name[14];
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};
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/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
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@@ -129,6 +139,7 @@ struct omap2_mcspi {
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struct omap2_mcspi_dma *dma_channels;
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struct device *dev;
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struct omap2_mcspi_regs ctx;
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+ int fifo_depth;
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unsigned int pin_dir:1;
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};
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@@ -187,6 +198,16 @@ static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
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mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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}
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+static inline int mcspi_bytes_per_word(int word_len)
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+{
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+ if (word_len <= 8)
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+ return 1;
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+ else if (word_len <= 16)
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+ return 2;
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+ else /* word_len <= 32 */
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+ return 4;
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+}
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+
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static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
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int is_read, int enable)
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{
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@@ -248,6 +269,58 @@ static void omap2_mcspi_set_master_mode(struct spi_master *master)
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ctx->modulctrl = l;
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}
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+static void omap2_mcspi_set_fifo(const struct spi_device *spi,
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+ struct spi_transfer *t, int enable)
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+{
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+ struct spi_master *master = spi->master;
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+ struct omap2_mcspi_cs *cs = spi->controller_state;
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+ struct omap2_mcspi *mcspi;
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+ unsigned int wcnt;
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+ int fifo_depth, bytes_per_word;
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+ u32 chconf, xferlevel;
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+
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+ mcspi = spi_master_get_devdata(master);
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+
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+ chconf = mcspi_cached_chconf0(spi);
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+ if (enable) {
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+ bytes_per_word = mcspi_bytes_per_word(cs->word_len);
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+ if (t->len % bytes_per_word != 0)
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+ goto disable_fifo;
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+
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+ fifo_depth = gcd(t->len, OMAP2_MCSPI_MAX_FIFODEPTH);
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+ if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
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+ goto disable_fifo;
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+
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+ wcnt = t->len / bytes_per_word;
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+ if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
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+ goto disable_fifo;
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+
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+ xferlevel = wcnt << 16;
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+ if (t->rx_buf != NULL) {
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+ chconf |= OMAP2_MCSPI_CHCONF_FFER;
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+ xferlevel |= (fifo_depth - 1) << 8;
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+ } else {
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+ chconf |= OMAP2_MCSPI_CHCONF_FFET;
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+ xferlevel |= fifo_depth - 1;
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+ }
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+
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+ mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
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+ mcspi_write_chconf0(spi, chconf);
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+ mcspi->fifo_depth = fifo_depth;
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+
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+ return;
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+ }
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+
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+disable_fifo:
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+ if (t->rx_buf != NULL)
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+ chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
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+ else
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+ chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
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+
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+ mcspi_write_chconf0(spi, chconf);
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+ mcspi->fifo_depth = 0;
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+}
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+
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static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
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{
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struct spi_master *spi_cntrl = mcspi->master;
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@@ -364,7 +437,7 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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{
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struct omap2_mcspi *mcspi;
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struct omap2_mcspi_dma *mcspi_dma;
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- unsigned int count;
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+ unsigned int count, dma_count;
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u32 l;
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int elements = 0;
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int word_len, element_count;
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@@ -372,6 +445,11 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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mcspi = spi_master_get_devdata(spi->master);
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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count = xfer->len;
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+ dma_count = xfer->len;
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+
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+ if (mcspi->fifo_depth == 0)
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+ dma_count -= es;
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+
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word_len = cs->word_len;
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l = mcspi_cached_chconf0(spi);
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@@ -385,16 +463,15 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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if (mcspi_dma->dma_rx) {
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struct dma_async_tx_descriptor *tx;
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struct scatterlist sg;
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- size_t len = xfer->len - es;
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dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
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- if (l & OMAP2_MCSPI_CHCONF_TURBO)
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- len -= es;
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+ if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
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+ dma_count -= es;
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sg_init_table(&sg, 1);
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sg_dma_address(&sg) = xfer->rx_dma;
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- sg_dma_len(&sg) = len;
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+ sg_dma_len(&sg) = dma_count;
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
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@@ -414,6 +491,10 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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wait_for_completion(&mcspi_dma->dma_rx_completion);
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dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
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DMA_FROM_DEVICE);
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+
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+ if (mcspi->fifo_depth > 0)
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+ return count;
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+
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omap2_mcspi_set_enable(spi, 0);
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elements = element_count - 1;
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@@ -433,10 +514,9 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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else /* word_len <= 32 */
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((u32 *)xfer->rx_buf)[elements++] = w;
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} else {
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+ int bytes_per_word = mcspi_bytes_per_word(word_len);
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dev_err(&spi->dev, "DMA RX penultimate word empty");
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- count -= (word_len <= 8) ? 2 :
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- (word_len <= 16) ? 4 :
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- /* word_len <= 32 */ 8;
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+ count -= (bytes_per_word << 1);
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omap2_mcspi_set_enable(spi, 1);
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return count;
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}
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@@ -454,9 +534,7 @@ omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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((u32 *)xfer->rx_buf)[elements] = w;
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} else {
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dev_err(&spi->dev, "DMA RX last word empty");
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- count -= (word_len <= 8) ? 1 :
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- (word_len <= 16) ? 2 :
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- /* word_len <= 32 */ 4;
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+ count -= mcspi_bytes_per_word(word_len);
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}
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omap2_mcspi_set_enable(spi, 1);
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return count;
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@@ -475,7 +553,10 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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struct dma_slave_config cfg;
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enum dma_slave_buswidth width;
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unsigned es;
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+ u32 burst;
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void __iomem *chstat_reg;
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+ void __iomem *irqstat_reg;
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+ int wait_res;
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mcspi = spi_master_get_devdata(spi->master);
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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@@ -493,19 +574,27 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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es = 4;
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}
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+ count = xfer->len;
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+ burst = 1;
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+
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+ if (mcspi->fifo_depth > 0) {
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+ if (count > mcspi->fifo_depth)
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+ burst = mcspi->fifo_depth / es;
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+ else
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+ burst = count / es;
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+ }
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+
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memset(&cfg, 0, sizeof(cfg));
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cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
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cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
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cfg.src_addr_width = width;
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cfg.dst_addr_width = width;
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- cfg.src_maxburst = 1;
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- cfg.dst_maxburst = 1;
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+ cfg.src_maxburst = burst;
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+ cfg.dst_maxburst = burst;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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- count = xfer->len;
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-
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if (tx != NULL)
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omap2_mcspi_tx_dma(spi, xfer, cfg);
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@@ -513,18 +602,38 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
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if (tx != NULL) {
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- chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
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wait_for_completion(&mcspi_dma->dma_tx_completion);
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dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
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DMA_TO_DEVICE);
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+ if (mcspi->fifo_depth > 0) {
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+ irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
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+
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+ if (mcspi_wait_for_reg_bit(irqstat_reg,
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+ OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
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+ dev_err(&spi->dev, "EOW timed out\n");
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+
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+ mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
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+ OMAP2_MCSPI_IRQSTATUS_EOW);
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+ }
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+
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/* for TX_ONLY mode, be sure all words have shifted out */
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if (rx == NULL) {
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- if (mcspi_wait_for_reg_bit(chstat_reg,
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- OMAP2_MCSPI_CHSTAT_TXS) < 0)
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- dev_err(&spi->dev, "TXS timed out\n");
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- else if (mcspi_wait_for_reg_bit(chstat_reg,
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- OMAP2_MCSPI_CHSTAT_EOT) < 0)
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+ chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
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+ if (mcspi->fifo_depth > 0) {
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+ wait_res = mcspi_wait_for_reg_bit(chstat_reg,
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+ OMAP2_MCSPI_CHSTAT_TXFFE);
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+ if (wait_res < 0)
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+ dev_err(&spi->dev, "TXFFE timed out\n");
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+ } else {
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+ wait_res = mcspi_wait_for_reg_bit(chstat_reg,
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+ OMAP2_MCSPI_CHSTAT_TXS);
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+ if (wait_res < 0)
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+ dev_err(&spi->dev, "TXS timed out\n");
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+ }
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+ if (wait_res >= 0 &&
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+ (mcspi_wait_for_reg_bit(chstat_reg,
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+ OMAP2_MCSPI_CHSTAT_EOT) < 0))
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dev_err(&spi->dev, "EOT timed out\n");
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}
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}
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@@ -830,12 +939,20 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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sig = mcspi_dma->dma_rx_sync_dev;
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- mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
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+
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+ mcspi_dma->dma_rx =
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+ dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
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+ &sig, &master->dev,
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+ mcspi_dma->dma_rx_ch_name);
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if (!mcspi_dma->dma_rx)
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goto no_dma;
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sig = mcspi_dma->dma_tx_sync_dev;
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- mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
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+ mcspi_dma->dma_tx =
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+ dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
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+ &sig, &master->dev,
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+ mcspi_dma->dma_tx_ch_name);
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+
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if (!mcspi_dma->dma_tx) {
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dma_release_channel(mcspi_dma->dma_rx);
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mcspi_dma->dma_rx = NULL;
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@@ -857,12 +974,6 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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struct omap2_mcspi_dma *mcspi_dma;
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struct omap2_mcspi_cs *cs = spi->controller_state;
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- if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
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- dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
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- spi->bits_per_word);
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- return -EINVAL;
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- }
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-
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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if (!cs) {
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@@ -951,7 +1062,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
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cs = spi->controller_state;
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cd = spi->controller_data;
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- omap2_mcspi_set_enable(spi, 1);
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+ omap2_mcspi_set_enable(spi, 0);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
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status = -EINVAL;
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@@ -999,6 +1110,12 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
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if (t->len) {
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unsigned count;
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+ if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
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+ (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
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+ omap2_mcspi_set_fifo(spi, t, 1);
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+
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+ omap2_mcspi_set_enable(spi, 1);
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+
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/* RX_ONLY mode needs dummy data in TX reg */
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if (t->tx_buf == NULL)
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__raw_writel(0, cs->base
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@@ -1025,6 +1142,11 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
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omap2_mcspi_force_cs(spi, 0);
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cs_active = 0;
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}
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+
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|
|
+ omap2_mcspi_set_enable(spi, 0);
|
|
|
+
|
|
|
+ if (mcspi->fifo_depth > 0)
|
|
|
+ omap2_mcspi_set_fifo(spi, t, 0);
|
|
|
}
|
|
|
/* Restore defaults if they were overriden */
|
|
|
if (par_override) {
|
|
@@ -1045,8 +1167,10 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
|
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
|
- m->status = status;
|
|
|
+ if (mcspi->fifo_depth > 0 && t)
|
|
|
+ omap2_mcspi_set_fifo(spi, t, 0);
|
|
|
|
|
|
+ m->status = status;
|
|
|
}
|
|
|
|
|
|
static int omap2_mcspi_transfer_one_message(struct spi_master *master,
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|
@@ -1072,10 +1196,7 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master,
|
|
|
unsigned len = t->len;
|
|
|
|
|
|
if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
|
|
|
- || (len && !(rx_buf || tx_buf))
|
|
|
- || (t->bits_per_word &&
|
|
|
- ( t->bits_per_word < 4
|
|
|
- || t->bits_per_word > 32))) {
|
|
|
+ || (len && !(rx_buf || tx_buf))) {
|
|
|
dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
|
|
|
t->speed_hz,
|
|
|
len,
|
|
@@ -1186,7 +1307,6 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
static int bus_num = 1;
|
|
|
struct device_node *node = pdev->dev.of_node;
|
|
|
const struct of_device_id *match;
|
|
|
- struct pinctrl *pinctrl;
|
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
|
|
|
if (master == NULL) {
|
|
@@ -1196,7 +1316,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
-
|
|
|
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
|
|
master->setup = omap2_mcspi_setup;
|
|
|
master->prepare_transfer_hardware = omap2_prepare_transfer;
|
|
|
master->unprepare_transfer_hardware = omap2_unprepare_transfer;
|
|
@@ -1204,7 +1324,7 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
master->cleanup = omap2_mcspi_cleanup;
|
|
|
master->dev.of_node = node;
|
|
|
|
|
|
- dev_set_drvdata(&pdev->dev, master);
|
|
|
+ platform_set_drvdata(pdev, master);
|
|
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
mcspi->master = master;
|
|
@@ -1256,39 +1376,47 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
goto free_master;
|
|
|
|
|
|
for (i = 0; i < master->num_chipselect; i++) {
|
|
|
- char dma_ch_name[14];
|
|
|
+ char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
|
|
|
+ char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
|
|
|
struct resource *dma_res;
|
|
|
|
|
|
- sprintf(dma_ch_name, "rx%d", i);
|
|
|
- dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
|
|
|
- dma_ch_name);
|
|
|
- if (!dma_res) {
|
|
|
- dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
|
|
|
- status = -ENODEV;
|
|
|
- break;
|
|
|
- }
|
|
|
+ sprintf(dma_rx_ch_name, "rx%d", i);
|
|
|
+ if (!pdev->dev.of_node) {
|
|
|
+ dma_res =
|
|
|
+ platform_get_resource_byname(pdev,
|
|
|
+ IORESOURCE_DMA,
|
|
|
+ dma_rx_ch_name);
|
|
|
+ if (!dma_res) {
|
|
|
+ dev_dbg(&pdev->dev,
|
|
|
+ "cannot get DMA RX channel\n");
|
|
|
+ status = -ENODEV;
|
|
|
+ break;
|
|
|
+ }
|
|
|
|
|
|
- mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
|
|
|
- sprintf(dma_ch_name, "tx%d", i);
|
|
|
- dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
|
|
|
- dma_ch_name);
|
|
|
- if (!dma_res) {
|
|
|
- dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
|
|
|
- status = -ENODEV;
|
|
|
- break;
|
|
|
+ mcspi->dma_channels[i].dma_rx_sync_dev =
|
|
|
+ dma_res->start;
|
|
|
}
|
|
|
+ sprintf(dma_tx_ch_name, "tx%d", i);
|
|
|
+ if (!pdev->dev.of_node) {
|
|
|
+ dma_res =
|
|
|
+ platform_get_resource_byname(pdev,
|
|
|
+ IORESOURCE_DMA,
|
|
|
+ dma_tx_ch_name);
|
|
|
+ if (!dma_res) {
|
|
|
+ dev_dbg(&pdev->dev,
|
|
|
+ "cannot get DMA TX channel\n");
|
|
|
+ status = -ENODEV;
|
|
|
+ break;
|
|
|
+ }
|
|
|
|
|
|
- mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
|
|
|
+ mcspi->dma_channels[i].dma_tx_sync_dev =
|
|
|
+ dma_res->start;
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
if (status < 0)
|
|
|
goto dma_chnl_free;
|
|
|
|
|
|
- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
|
|
- if (IS_ERR(pinctrl))
|
|
|
- dev_warn(&pdev->dev,
|
|
|
- "pins are not configured from the driver\n");
|
|
|
-
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
@@ -1318,7 +1446,7 @@ static int omap2_mcspi_remove(struct platform_device *pdev)
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
struct omap2_mcspi_dma *dma_channels;
|
|
|
|
|
|
- master = dev_get_drvdata(&pdev->dev);
|
|
|
+ master = platform_get_drvdata(pdev);
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
dma_channels = mcspi->dma_channels;
|
|
|
|