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@@ -1151,7 +1151,8 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
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ah->mask_reg |= AR_IMR_MIB;
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REG_WRITE(ah, AR_IMR, ah->mask_reg);
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- REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
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+ ah->imrs2_reg |= AR_IMR_S2_GTT;
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+ REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
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if (!AR_SREV_9100(ah)) {
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REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
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@@ -2920,14 +2921,11 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
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ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
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REG_WRITE(ah, AR_IMR, mask);
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- mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
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- AR_IMR_S2_DTIM |
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- AR_IMR_S2_DTIMSYNC |
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- AR_IMR_S2_CABEND |
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- AR_IMR_S2_CABTO |
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- AR_IMR_S2_TSFOOR |
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- AR_IMR_S2_GTT | AR_IMR_S2_CST);
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- REG_WRITE(ah, AR_IMR_S2, mask | mask2);
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+ ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
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+ AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
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+ AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
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+ ah->imrs2_reg |= mask2;
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+ REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
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ah->mask_reg = ints;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
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