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@@ -116,6 +116,7 @@
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/* Clock registers available only on Version 2 */
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#define LCD_CLK_ENABLE_REG 0x6c
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#define LCD_CLK_RESET_REG 0x70
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+#define LCD_CLK_MAIN_RESET BIT(3)
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#define LCD_NUM_BUFFERS 2
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@@ -244,6 +245,10 @@ static inline void lcd_enable_raster(void)
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{
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u32 reg;
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+ /* Bring LCDC out of reset */
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+ if (lcd_revision == LCD_VERSION_2)
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+ lcdc_write(0, LCD_CLK_RESET_REG);
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+
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reg = lcdc_read(LCD_RASTER_CTRL_REG);
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if (!(reg & LCD_RASTER_ENABLE))
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lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
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@@ -257,6 +262,10 @@ static inline void lcd_disable_raster(void)
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reg = lcdc_read(LCD_RASTER_CTRL_REG);
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if (reg & LCD_RASTER_ENABLE)
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lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
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+
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+ if (lcd_revision == LCD_VERSION_2)
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+ /* Write 1 to reset LCDC */
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+ lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
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}
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static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
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@@ -584,8 +593,12 @@ static void lcd_reset(struct da8xx_fb_par *par)
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lcdc_write(0, LCD_DMA_CTRL_REG);
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lcdc_write(0, LCD_RASTER_CTRL_REG);
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- if (lcd_revision == LCD_VERSION_2)
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+ if (lcd_revision == LCD_VERSION_2) {
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lcdc_write(0, LCD_INT_ENABLE_SET_REG);
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+ /* Write 1 to reset */
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+ lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
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+ lcdc_write(0, LCD_CLK_RESET_REG);
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+ }
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}
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static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
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