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@@ -0,0 +1,275 @@
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+/*
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+ * Copyright 2007-8 Advanced Micro Devices, Inc.
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+ * Copyright 2008 Red Hat Inc.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * Authors: Dave Airlie
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+ * Alex Deucher
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+ */
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+#include "drmP.h"
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+#include "radeon_drm.h"
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+#include "radeon.h"
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+
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+#include "atom.h"
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+#include "atom-bits.h"
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+#include "drm_dp_helper.h"
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+
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+#define DP_LINK_STATUS_SIZE 6
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+
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+bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
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+ int num_bytes, u8 *read_byte,
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+ u8 read_buf_len, u8 delay)
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+{
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+ struct drm_device *dev = chan->dev;
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+ struct radeon_device *rdev = dev->dev_private;
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+ PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
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+ int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
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+ unsigned char *base;
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+
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+ memset(&args, 0, sizeof(args));
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+
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+ base = (unsigned char *)rdev->mode_info.atom_context->scratch;
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+
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+ memcpy(base, req_bytes, num_bytes);
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+
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+ args.lpAuxRequest = 0;
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+ args.lpDataOut = 16;
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+ args.ucDataOutLen = 0;
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+ args.ucChannelID = chan->i2c_id;
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+ args.ucDelay = delay;
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+
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+ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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+
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+ if (args.ucReplyStatus) {
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+ DRM_ERROR("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
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+ req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
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+ chan->i2c_id, args.ucReplyStatus);
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+ return false;
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+ }
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+
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+ if (args.ucDataOutLen && read_byte && read_buf_len) {
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+ if (read_buf_len < args.ucDataOutLen) {
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+ DRM_ERROR("Buffer to small for return answer %d %d\n",
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+ read_buf_len, args.ucDataOutLen);
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+ return false;
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+ }
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+ {
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+ int len = min(read_buf_len, args.ucDataOutLen);
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+ memcpy(read_byte, base + 16, len);
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+ }
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+ }
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+ return true;
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+}
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+
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+int radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
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+ uint8_t ucconfig, uint8_t lane_num)
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+{
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+ DP_ENCODER_SERVICE_PARAMETERS args;
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+ int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
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+
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+ memset(&args, 0, sizeof(args));
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+ args.ucLinkClock = dp_clock / 10;
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+ args.ucConfig = ucconfig;
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+ args.ucAction = action;
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+ args.ucLaneNum = lane_num;
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+ args.ucStatus = 0;
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+
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+ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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+ return args.ucStatus;
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+}
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+
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+int radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
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+{
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+ struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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+ struct drm_device *dev = radeon_connector->base.dev;
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+ struct radeon_device *rdev = dev->dev_private;
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+
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+ return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
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+ radeon_dig_connector->uc_i2c_id, 0);
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+}
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+
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+union dig_transmitter_control {
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+ DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
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+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
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+};
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+
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+bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
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+ uint8_t send_bytes, uint8_t *send)
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+{
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+ struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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+ struct drm_device *dev = radeon_connector->base.dev;
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+ struct radeon_device *rdev = dev->dev_private;
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+ u8 msg[20];
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+ u8 msg_len, dp_msg_len;
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+ bool ret;
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+
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+ dp_msg_len = 4;
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+ msg[0] = address;
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+ msg[1] = address >> 8;
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+ msg[2] = AUX_NATIVE_WRITE << 4;
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+ dp_msg_len += send_bytes;
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+ msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
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+
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+ if (send_bytes > 16)
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+ return false;
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+
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+ memcpy(&msg[4], send, send_bytes);
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+ msg_len = 4 + send_bytes;
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+ ret = radeon_process_aux_ch(radeon_dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
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+ return ret;
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+}
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+
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+bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address,
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+ uint8_t delay, uint8_t expected_bytes,
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+ uint8_t *read_p)
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+{
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+ struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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+ struct drm_device *dev = radeon_connector->base.dev;
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+ struct radeon_device *rdev = dev->dev_private;
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+ u8 msg[20];
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+ u8 msg_len, dp_msg_len;
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+ bool ret = false;
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+ msg_len = 4;
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+ dp_msg_len = 4;
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+ msg[0] = address;
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+ msg[1] = address >> 8;
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+ msg[2] = AUX_NATIVE_READ << 4;
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+ msg[3] = (dp_msg_len) << 4;
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+ msg[3] |= expected_bytes - 1;
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+
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+ ret = radeon_process_aux_ch(radeon_dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
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+ return ret;
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+}
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+
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+void radeon_dp_getdpcp(struct radeon_connector *radeon_connector)
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+{
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+ struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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+ u8 msg[25];
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+ int ret;
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+
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+ ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCP_REV, 0, 8, msg);
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+ if (ret) {
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+ memcpy(radeon_dig_connector->dpcp, msg, 8);
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+ {
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+ int i;
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+ printk("DPCP: ");
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+ for (i = 0; i < 8; i++)
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+ printk("%02x ", msg[i]);
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+ printk("\n");
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+ }
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+ }
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+ radeon_dig_connector->dpcp[0] = 0;
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+ return;
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+}
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+
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+static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
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+ u8 link_status[DP_LINK_STATUS_SIZE])
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+{
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+ int ret;
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+ ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100,
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+ DP_LINK_STATUS_SIZE, link_status);
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+ if (!ret) {
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+ DRM_ERROR("displayport link status failed\n");
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+ return false;
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+ }
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+
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+ DRM_INFO("link status %02x %02x %02x %02x %02x %02x\n",
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+ link_status[0], link_status[1], link_status[2],
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+ link_status[3], link_status[4], link_status[5]);
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+ return true;
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+}
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+
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+static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
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+{
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+ struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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+ if (radeon_dig_connector->dpcp[0] >= 0x11) {
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+ radeon_dp_aux_native_write(radeon_connector, 0x600, 1,
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+ &power_state);
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+ }
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+}
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+
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+static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
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+ u8 train_set[4])
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+{
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+ struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
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+
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+// radeon_dp_digtransmitter_setup_vsemph();
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+ radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
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+ 0/* lc */, train_set);
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+}
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+
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+static void dp_set_training(struct radeon_connector *radeon_connector,
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+ u8 training)
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+{
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+ radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
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+ 1, &training);
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+}
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+
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+int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
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+ uint8_t write_byte, uint8_t *read_byte)
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+{
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+ struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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+ struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
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+ int ret = 0;
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+ uint16_t address = algo_data->address;
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+ uint8_t msg[5];
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+ uint8_t reply[2];
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+ int msg_len, dp_msg_len;
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+ int reply_bytes;
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+
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+ /* Set up the command byte */
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+ if (mode & MODE_I2C_READ)
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+ msg[2] = AUX_I2C_READ << 4;
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+ else
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+ msg[2] = AUX_I2C_WRITE << 4;
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+
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+ if (!(mode & MODE_I2C_STOP))
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+ msg[2] |= AUX_I2C_MOT << 4;
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+
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+ msg[0] = address;
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+ msg[1] = address >> 8;
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+
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+ reply_bytes = 1;
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+
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+ msg_len = 4;
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+ dp_msg_len = 3;
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+ switch (mode) {
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+ case MODE_I2C_WRITE:
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+ msg[4] = write_byte;
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+ msg_len++;
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+ dp_msg_len += 2;
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+ break;
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+ case MODE_I2C_READ:
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+ dp_msg_len += 1;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ msg[3] = (dp_msg_len) << 4;
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+ ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0);
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+
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+ if (ret) {
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+ if (read_byte)
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+ *read_byte = reply[0];
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+ return reply_bytes;
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+ }
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+ return -EREMOTEIO;
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+}
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Dave Airlie