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@@ -43,6 +43,8 @@ static struct ide_timing ide_timing[] = {
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{ XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
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{ XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
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+ { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 },
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+ { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 },
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{ XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
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{ XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
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{ XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
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@@ -51,7 +53,8 @@ static struct ide_timing ide_timing[] = {
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{ XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
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{ XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
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- { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 },
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+ { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 },
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+ { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 },
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{ XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
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{ XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
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@@ -90,6 +93,10 @@ u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio)
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/* conservative "downgrade" for all pre-ATA2 drives */
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if (pio < 3 && cycle < t->cycle)
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cycle = 0; /* use standard timing */
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+
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+ /* Use the standard timing for the CF specific modes too */
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+ if (pio > 4 && ata_id_is_cfa(id))
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+ cycle = 0;
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}
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return cycle ? cycle : t->cycle;
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@@ -161,7 +168,8 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed,
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if (speed <= XFER_PIO_2)
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p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
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- else if (speed <= XFER_PIO_5)
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+ else if ((speed <= XFER_PIO_4) ||
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+ (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
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p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
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else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
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p.cycle = id[ATA_ID_EIDE_DMA_MIN];
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