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@@ -93,19 +93,19 @@ static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
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u32 cpu_ctrl;
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/* 10.5.0 run the firmware (I) */
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- cpu_ctrl = wl1271_reg_read32(wl, ACX_REG_ECPU_CONTROL);
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+ cpu_ctrl = wl1271_spi_read32(wl, ACX_REG_ECPU_CONTROL);
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/* 10.5.1 run the firmware (II) */
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cpu_ctrl |= flag;
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- wl1271_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
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+ wl1271_spi_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
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}
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static void wl1271_boot_fw_version(struct wl1271 *wl)
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{
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struct wl1271_static_data static_data;
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- wl1271_spi_mem_read(wl, wl->cmd_box_addr,
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- &static_data, sizeof(static_data));
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+ wl1271_spi_read(wl, wl->cmd_box_addr,
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+ &static_data, sizeof(static_data), false);
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strncpy(wl->chip.fw_ver, static_data.fw_version,
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sizeof(wl->chip.fw_ver));
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@@ -164,7 +164,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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memcpy(chunk, p, CHUNK_SIZE);
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wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
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p, addr);
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- wl1271_spi_mem_write(wl, addr, chunk, CHUNK_SIZE);
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+ wl1271_spi_write(wl, addr, chunk, CHUNK_SIZE, false);
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chunk_num++;
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}
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@@ -175,7 +175,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
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wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
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fw_data_len % CHUNK_SIZE, p, addr);
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- wl1271_spi_mem_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE);
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+ wl1271_spi_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
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kfree(chunk);
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return 0;
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@@ -262,7 +262,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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wl1271_debug(DEBUG_BOOT,
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"nvs burst write 0x%x: 0x%x",
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dest_addr, val);
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- wl1271_reg_write32(wl, dest_addr, val);
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+ wl1271_spi_write32(wl, dest_addr, val);
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nvs_ptr += 4;
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dest_addr += 4;
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@@ -289,7 +289,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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/* FIXME: In wl1271, we upload everything at once.
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No endianness handling needed here?! The ref driver doesn't do
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anything about it at this point */
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- wl1271_spi_mem_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len);
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+ wl1271_spi_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
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kfree(nvs_aligned);
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return 0;
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@@ -298,9 +298,9 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
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{
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enable_irq(wl->irq);
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- wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
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+ wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
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WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
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- wl1271_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
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+ wl1271_spi_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
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}
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static int wl1271_boot_soft_reset(struct wl1271 *wl)
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@@ -309,12 +309,13 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl)
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u32 boot_data;
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/* perform soft reset */
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- wl1271_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
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+ wl1271_spi_write32(wl, ACX_REG_SLV_SOFT_RESET,
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+ ACX_SLV_SOFT_RESET_BIT);
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/* SOFT_RESET is self clearing */
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timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
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while (1) {
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- boot_data = wl1271_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
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+ boot_data = wl1271_spi_read32(wl, ACX_REG_SLV_SOFT_RESET);
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wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
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if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
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break;
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@@ -330,10 +331,10 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl)
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}
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/* disable Rx/Tx */
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- wl1271_reg_write32(wl, ENABLE, 0x0);
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+ wl1271_spi_write32(wl, ENABLE, 0x0);
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/* disable auto calibration on start*/
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- wl1271_reg_write32(wl, SPARE_A2, 0xffff);
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+ wl1271_spi_write32(wl, SPARE_A2, 0xffff);
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return 0;
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}
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@@ -345,7 +346,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
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- chip_id = wl1271_reg_read32(wl, CHIP_ID_B);
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+ chip_id = wl1271_spi_read32(wl, CHIP_ID_B);
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wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
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@@ -358,7 +359,8 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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loop = 0;
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while (loop++ < INIT_LOOP) {
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udelay(INIT_LOOP_DELAY);
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- interrupt = wl1271_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
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+ interrupt = wl1271_spi_read32(wl,
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+ ACX_REG_INTERRUPT_NO_CLEAR);
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if (interrupt == 0xffffffff) {
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wl1271_error("error reading hardware complete "
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@@ -367,7 +369,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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}
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/* check that ACX_INTR_INIT_COMPLETE is enabled */
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else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
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- wl1271_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
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+ wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK,
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WL1271_ACX_INTR_INIT_COMPLETE);
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break;
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}
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@@ -380,10 +382,10 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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}
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/* get hardware config command mail box */
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- wl->cmd_box_addr = wl1271_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
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+ wl->cmd_box_addr = wl1271_spi_read32(wl, REG_COMMAND_MAILBOX_PTR);
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/* get hardware config event mail box */
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- wl->event_box_addr = wl1271_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
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+ wl->event_box_addr = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR);
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/* set the working partition to its "running" mode offset */
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wl1271_set_partition(wl, &part_table[PART_WORK]);
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@@ -458,9 +460,9 @@ int wl1271_boot(struct wl1271 *wl)
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wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
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}
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- wl1271_reg_write32(wl, PLL_PARAMETERS, clk);
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+ wl1271_spi_write32(wl, PLL_PARAMETERS, clk);
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- pause = wl1271_reg_read32(wl, PLL_PARAMETERS);
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+ pause = wl1271_spi_read32(wl, PLL_PARAMETERS);
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wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
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@@ -469,10 +471,10 @@ int wl1271_boot(struct wl1271 *wl)
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* 0x3ff (magic number ). How does
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* this work?! */
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pause |= WU_COUNTER_PAUSE_VAL;
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- wl1271_reg_write32(wl, WU_COUNTER_PAUSE, pause);
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+ wl1271_spi_write32(wl, WU_COUNTER_PAUSE, pause);
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/* Continue the ELP wake up sequence */
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- wl1271_reg_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
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+ wl1271_spi_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
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udelay(500);
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wl1271_set_partition(wl, &part_table[PART_DRPW]);
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@@ -482,18 +484,18 @@ int wl1271_boot(struct wl1271 *wl)
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before taking DRPw out of reset */
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wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
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- clk = wl1271_reg_read32(wl, DRPW_SCRATCH_START);
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+ clk = wl1271_spi_read32(wl, DRPW_SCRATCH_START);
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wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
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/* 2 */
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clk |= (REF_CLOCK << 1) << 4;
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- wl1271_reg_write32(wl, DRPW_SCRATCH_START, clk);
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+ wl1271_spi_write32(wl, DRPW_SCRATCH_START, clk);
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wl1271_set_partition(wl, &part_table[PART_WORK]);
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/* Disable interrupts */
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- wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
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+ wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
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ret = wl1271_boot_soft_reset(wl);
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if (ret < 0)
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@@ -508,21 +510,22 @@ int wl1271_boot(struct wl1271 *wl)
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* ACX_EEPROMLESS_IND_REG */
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wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
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- wl1271_reg_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
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+ wl1271_spi_write32(wl, ACX_EEPROMLESS_IND_REG,
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+ ACX_EEPROMLESS_IND_REG);
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- tmp = wl1271_reg_read32(wl, CHIP_ID_B);
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+ tmp = wl1271_spi_read32(wl, CHIP_ID_B);
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wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
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/* 6. read the EEPROM parameters */
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- tmp = wl1271_reg_read32(wl, SCR_PAD2);
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+ tmp = wl1271_spi_read32(wl, SCR_PAD2);
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ret = wl1271_boot_write_irq_polarity(wl);
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if (ret < 0)
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goto out;
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/* FIXME: Need to check whether this is really what we want */
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- wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
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+ wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
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WL1271_ACX_ALL_EVENTS_VECTOR);
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/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
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