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@@ -267,7 +267,8 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
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#define RIRB_INT_MASK 0x05
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/* STATESTS int mask: S3,SD2,SD1,SD0 */
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-#define AZX_MAX_CODECS 4
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+#define AZX_MAX_CODECS 8
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+#define AZX_DEFAULT_CODECS 4
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#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
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/* SD_CTL bits */
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@@ -1367,6 +1368,7 @@ static void azx_bus_reset(struct hda_bus *bus)
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/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
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static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
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+ [AZX_DRIVER_NVIDIA] = 8,
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[AZX_DRIVER_TERA] = 1,
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};
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@@ -1399,7 +1401,7 @@ static int __devinit azx_codec_create(struct azx *chip, const char *model)
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codecs = 0;
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max_slots = azx_max_codecs[chip->driver_type];
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if (!max_slots)
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- max_slots = AZX_MAX_CODECS;
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+ max_slots = AZX_DEFAULT_CODECS;
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/* First try to probe all given codec slots */
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for (c = 0; c < max_slots; c++) {
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