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@@ -559,11 +559,15 @@ ENTRY(fsys_getcpu)
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;;
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tnat.nz p7,p0 = r33 // I guard against NaT argument
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(p7) br.cond.spnt.few .fail_einval // B
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+ ;;
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+ cmp.ne p6,p0=r32,r0
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+ cmp.ne p7,p0=r33,r0
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+ ;;
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#ifdef CONFIG_NUMA
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movl r17=cpu_to_node_map
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;;
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-EX(.fail_efault, probe.w.fault r32, 3) // M This takes 5 cycles
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-EX(.fail_efault, probe.w.fault r33, 3) // M This takes 5 cycles
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+EX(.fail_efault, (p6) probe.w.fault r32, 3) // M This takes 5 cycles
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+EX(.fail_efault, (p7) probe.w.fault r33, 3) // M This takes 5 cycles
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shladd r18=r3,1,r17
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;;
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ld2 r20=[r18] // r20 = cpu_to_node_map[cpu]
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@@ -573,20 +577,20 @@ EX(.fail_efault, probe.w.fault r33, 3) // M This takes 5 cycles
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(p8) br.spnt.many fsys_fallback_syscall
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;;
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;;
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-EX(.fail_efault, st4 [r32] = r3)
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-EX(.fail_efault, st2 [r33] = r20)
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+EX(.fail_efault, (p6) st4 [r32] = r3)
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+EX(.fail_efault, (p7) st2 [r33] = r20)
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mov r8=0
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;;
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#else
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-EX(.fail_efault, probe.w.fault r32, 3) // M This takes 5 cycles
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-EX(.fail_efault, probe.w.fault r33, 3) // M This takes 5 cycles
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+EX(.fail_efault, (p6) probe.w.fault r32, 3) // M This takes 5 cycles
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+EX(.fail_efault, (p7) probe.w.fault r33, 3) // M This takes 5 cycles
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and r2 = TIF_ALLWORK_MASK,r2
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;;
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cmp.ne p8,p0=0,r2
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(p8) br.spnt.many fsys_fallback_syscall
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;;
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-EX(.fail_efault, st4 [r32] = r3)
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-EX(.fail_efault, st2 [r33] = r0)
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+EX(.fail_efault, (p6) st4 [r32] = r3)
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+EX(.fail_efault, (p7) st2 [r33] = r0)
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mov r8=0
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;;
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#endif
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