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@@ -298,7 +298,7 @@ x86_perf_event_update(struct perf_event *event)
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*/
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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- rdmsrl(hwc->event_base + idx, new_raw_count);
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+ rdmsrl(hwc->event_base, new_raw_count);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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@@ -655,7 +655,7 @@ static void x86_pmu_disable(struct pmu *pmu)
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static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
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u64 enable_mask)
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{
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- wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
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+ wrmsrl(hwc->config_base, hwc->config | enable_mask);
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}
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static void x86_pmu_enable_all(int added)
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@@ -834,15 +834,10 @@ static inline void x86_assign_hw_event(struct perf_event *event,
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hwc->event_base = 0;
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} else if (hwc->idx >= X86_PMC_IDX_FIXED) {
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hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
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- /*
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- * We set it so that event_base + idx in wrmsr/rdmsr maps to
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- * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
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- */
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- hwc->event_base =
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- MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
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+ hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0;
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} else {
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- hwc->config_base = x86_pmu.eventsel;
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- hwc->event_base = x86_pmu.perfctr;
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+ hwc->config_base = x86_pmu_config_addr(hwc->idx);
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+ hwc->event_base = x86_pmu_event_addr(hwc->idx);
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}
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}
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@@ -932,7 +927,7 @@ static inline void x86_pmu_disable_event(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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- wrmsrl(hwc->config_base + hwc->idx, hwc->config);
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+ wrmsrl(hwc->config_base, hwc->config);
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}
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static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
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@@ -985,7 +980,7 @@ x86_perf_event_set_period(struct perf_event *event)
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*/
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local64_set(&hwc->prev_count, (u64)-left);
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- wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
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+ wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
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/*
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* Due to erratum on certan cpu we need
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@@ -993,7 +988,7 @@ x86_perf_event_set_period(struct perf_event *event)
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* is updated properly
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*/
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if (x86_pmu.perfctr_second_write) {
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- wrmsrl(hwc->event_base + idx,
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+ wrmsrl(hwc->event_base,
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(u64)(-left) & x86_pmu.cntval_mask);
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}
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