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@@ -62,6 +62,15 @@
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#include <asm/reboot.h>
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#include <asm/stackprotector.h>
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#include <asm/hypervisor.h>
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+#include <asm/mwait.h>
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+
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+#ifdef CONFIG_ACPI
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+#include <linux/acpi.h>
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+#include <asm/acpi.h>
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+#include <acpi/pdc_intel.h>
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+#include <acpi/processor.h>
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+#include <xen/interface/platform.h>
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+#endif
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#include "xen-ops.h"
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#include "mmu.h"
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@@ -200,13 +209,17 @@ static void __init xen_banner(void)
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static __read_mostly unsigned int cpuid_leaf1_edx_mask = ~0;
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static __read_mostly unsigned int cpuid_leaf1_ecx_mask = ~0;
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+static __read_mostly unsigned int cpuid_leaf1_ecx_set_mask;
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+static __read_mostly unsigned int cpuid_leaf5_ecx_val;
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+static __read_mostly unsigned int cpuid_leaf5_edx_val;
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+
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static void xen_cpuid(unsigned int *ax, unsigned int *bx,
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unsigned int *cx, unsigned int *dx)
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{
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unsigned maskebx = ~0;
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unsigned maskecx = ~0;
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unsigned maskedx = ~0;
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-
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+ unsigned setecx = 0;
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/*
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* Mask out inconvenient features, to try and disable as many
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* unsupported kernel subsystems as possible.
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@@ -214,9 +227,18 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
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switch (*ax) {
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case 1:
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maskecx = cpuid_leaf1_ecx_mask;
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+ setecx = cpuid_leaf1_ecx_set_mask;
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maskedx = cpuid_leaf1_edx_mask;
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break;
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+ case CPUID_MWAIT_LEAF:
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+ /* Synthesize the values.. */
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+ *ax = 0;
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+ *bx = 0;
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+ *cx = cpuid_leaf5_ecx_val;
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+ *dx = cpuid_leaf5_edx_val;
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+ return;
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+
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case 0xb:
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/* Suppress extended topology stuff */
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maskebx = 0;
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@@ -232,9 +254,75 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
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*bx &= maskebx;
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*cx &= maskecx;
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+ *cx |= setecx;
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*dx &= maskedx;
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+
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}
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+static bool __init xen_check_mwait(void)
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+{
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+#ifdef CONFIG_ACPI
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+ struct xen_platform_op op = {
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+ .cmd = XENPF_set_processor_pminfo,
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+ .u.set_pminfo.id = -1,
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+ .u.set_pminfo.type = XEN_PM_PDC,
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+ };
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+ uint32_t buf[3];
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+ unsigned int ax, bx, cx, dx;
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+ unsigned int mwait_mask;
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+
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+ /* We need to determine whether it is OK to expose the MWAIT
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+ * capability to the kernel to harvest deeper than C3 states from ACPI
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+ * _CST using the processor_harvest_xen.c module. For this to work, we
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+ * need to gather the MWAIT_LEAF values (which the cstate.c code
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+ * checks against). The hypervisor won't expose the MWAIT flag because
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+ * it would break backwards compatibility; so we will find out directly
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+ * from the hardware and hypercall.
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+ */
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+ if (!xen_initial_domain())
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+ return false;
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+
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+ ax = 1;
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+ cx = 0;
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+
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+ native_cpuid(&ax, &bx, &cx, &dx);
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+
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+ mwait_mask = (1 << (X86_FEATURE_EST % 32)) |
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+ (1 << (X86_FEATURE_MWAIT % 32));
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+
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+ if ((cx & mwait_mask) != mwait_mask)
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+ return false;
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+
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+ /* We need to emulate the MWAIT_LEAF and for that we need both
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+ * ecx and edx. The hypercall provides only partial information.
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+ */
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+
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+ ax = CPUID_MWAIT_LEAF;
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+ bx = 0;
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+ cx = 0;
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+ dx = 0;
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+
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+ native_cpuid(&ax, &bx, &cx, &dx);
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+
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+ /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so,
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+ * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3.
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+ */
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+ buf[0] = ACPI_PDC_REVISION_ID;
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+ buf[1] = 1;
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+ buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP);
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+
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+ set_xen_guest_handle(op.u.set_pminfo.pdc, buf);
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+
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+ if ((HYPERVISOR_dom0_op(&op) == 0) &&
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+ (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) {
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+ cpuid_leaf5_ecx_val = cx;
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+ cpuid_leaf5_edx_val = dx;
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+ }
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+ return true;
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+#else
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+ return false;
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+#endif
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+}
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static void __init xen_init_cpuid_mask(void)
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{
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unsigned int ax, bx, cx, dx;
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@@ -261,6 +349,9 @@ static void __init xen_init_cpuid_mask(void)
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/* Xen will set CR4.OSXSAVE if supported and not disabled by force */
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if ((cx & xsave_mask) != xsave_mask)
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cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
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+
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+ if (xen_check_mwait())
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+ cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
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}
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static void xen_set_debugreg(int reg, unsigned long val)
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