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@@ -232,7 +232,7 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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- u32 base_rate = 48000;
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+ u32 base_rate = 24000;
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if (!dig || !dig->afmt)
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return;
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@@ -240,7 +240,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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/* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
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* doesn't matter which one you use. Just use the first one.
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*/
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- /* XXX: properly calculate this */
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/* XXX two dtos; generally use dto0 for hdmi */
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/* Express [24MHz / target pixel clock] as an exact rational
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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@@ -250,13 +249,13 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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/* according to the reg specs, this should DCE3.2 only, but in
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* practice it seems to cover DCE3.0 as well.
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*/
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- WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50);
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+ WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
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WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
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WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
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} else {
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/* according to the reg specs, this should be DCE2.0 and DCE3.0 */
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- WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) |
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- AUDIO_DTO_MODULE(clock * 100));
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+ WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
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+ AUDIO_DTO_MODULE(clock / 10));
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}
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}
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