|
@@ -61,7 +61,6 @@ static struct irq_domain *armada_370_xp_mpic_domain;
|
|
|
*/
|
|
|
static void armada_370_xp_irq_mask(struct irq_data *d)
|
|
|
{
|
|
|
-#ifdef CONFIG_SMP
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
|
|
|
|
|
if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
|
|
@@ -70,15 +69,10 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
|
|
|
else
|
|
|
writel(hwirq, per_cpu_int_base +
|
|
|
ARMADA_370_XP_INT_SET_MASK_OFFS);
|
|
|
-#else
|
|
|
- writel(irqd_to_hwirq(d),
|
|
|
- per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
|
|
|
-#endif
|
|
|
}
|
|
|
|
|
|
static void armada_370_xp_irq_unmask(struct irq_data *d)
|
|
|
{
|
|
|
-#ifdef CONFIG_SMP
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
|
|
|
|
|
if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
|
|
@@ -87,10 +81,6 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
|
|
|
else
|
|
|
writel(hwirq, per_cpu_int_base +
|
|
|
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
-#else
|
|
|
- writel(irqd_to_hwirq(d),
|
|
|
- per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
-#endif
|
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
@@ -146,7 +136,11 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
|
|
|
unsigned int virq, irq_hw_number_t hw)
|
|
|
{
|
|
|
armada_370_xp_irq_mask(irq_get_irq_data(virq));
|
|
|
- writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
|
|
+ if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
|
|
|
+ writel(hw, per_cpu_int_base +
|
|
|
+ ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
+ else
|
|
|
+ writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
|
|
irq_set_status_flags(virq, IRQ_LEVEL);
|
|
|
|
|
|
if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
|