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@@ -577,7 +577,6 @@ static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
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static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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struct pl08x_txd *txd)
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struct pl08x_txd *txd)
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{
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{
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- struct pl08x_channel_data *cd = txd->cd;
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struct pl08x_bus_data *mbus, *sbus;
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struct pl08x_bus_data *mbus, *sbus;
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size_t remainder;
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size_t remainder;
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int num_llis = 0;
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int num_llis = 0;
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@@ -595,17 +594,8 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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pl08x->pool_ctr++;
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pl08x->pool_ctr++;
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- /*
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- * Initialize bus values for this transfer
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- * from the passed optimal values
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- */
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- if (!cd) {
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- dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
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- return 0;
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- }
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-
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- /* Get the default CCTL from the platform data */
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- cctl = cd->cctl;
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+ /* Get the default CCTL */
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+ cctl = txd->cctl;
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/*
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/*
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* On the PL080 we have two bus masters and we
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* On the PL080 we have two bus masters and we
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@@ -1358,11 +1348,11 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
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txd->dstbus.addr = dest;
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txd->dstbus.addr = dest;
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/* Set platform data for m2m */
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/* Set platform data for m2m */
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- txd->cd = &pl08x->pd->memcpy_channel;
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txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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+ txd->cctl = pl08x->pd->memcpy_channel.cctl;
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/* Both to be incremented or the code will break */
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/* Both to be incremented or the code will break */
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- txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
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+ txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
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txd->len = len;
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txd->len = len;
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ret = pl08x_prep_channel_resources(plchan, txd);
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ret = pl08x_prep_channel_resources(plchan, txd);
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@@ -1415,6 +1405,8 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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* channel target address dynamically at runtime.
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* channel target address dynamically at runtime.
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*/
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*/
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txd->direction = direction;
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txd->direction = direction;
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+ txd->cctl = plchan->cd->cctl;
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+
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if (direction == DMA_TO_DEVICE) {
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if (direction == DMA_TO_DEVICE) {
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txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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txd->srcbus.addr = sgl->dma_address;
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txd->srcbus.addr = sgl->dma_address;
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@@ -1434,7 +1426,6 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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"%s direction unsupported\n", __func__);
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"%s direction unsupported\n", __func__);
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return NULL;
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return NULL;
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}
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}
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- txd->cd = plchan->cd;
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txd->len = sgl->length;
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txd->len = sgl->length;
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ret = pl08x_prep_channel_resources(plchan, txd);
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ret = pl08x_prep_channel_resources(plchan, txd);
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