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+/*
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+ * dw_spi_mid.c - special handling for DW core on Intel MID platform
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+ *
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+ * Copyright (c) 2009, Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation,
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+ * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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+ */
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+
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+#include <linux/dma-mapping.h>
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+#include <linux/dmaengine.h>
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+#include <linux/interrupt.h>
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+#include <linux/slab.h>
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+#include <linux/spi/spi.h>
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+#include <linux/spi/dw_spi.h>
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+
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+#ifdef CONFIG_SPI_DW_MID_DMA
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+#include <linux/intel_mid_dma.h>
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+#include <linux/pci.h>
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+
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+struct mid_dma {
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+ struct intel_mid_dma_slave dmas_tx;
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+ struct intel_mid_dma_slave dmas_rx;
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+};
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+
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+static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
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+{
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+ struct dw_spi *dws = param;
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+
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+ return dws->dmac && (&dws->dmac->dev == chan->device->dev);
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+}
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+
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+static int mid_spi_dma_init(struct dw_spi *dws)
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+{
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+ struct mid_dma *dw_dma = dws->dma_priv;
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+ struct intel_mid_dma_slave *rxs, *txs;
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+ dma_cap_mask_t mask;
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+
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+ /*
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+ * Get pci device for DMA controller, currently it could only
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+ * be the DMA controller of either Moorestown or Medfield
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+ */
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+ dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0813, NULL);
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+ if (!dws->dmac)
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+ dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
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+
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+ dma_cap_zero(mask);
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+ dma_cap_set(DMA_SLAVE, mask);
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+
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+ /* 1. Init rx channel */
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+ dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
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+ if (!dws->rxchan)
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+ goto err_exit;
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+ rxs = &dw_dma->dmas_rx;
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+ rxs->hs_mode = LNW_DMA_HW_HS;
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+ rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
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+ dws->rxchan->private = rxs;
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+
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+ /* 2. Init tx channel */
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+ dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
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+ if (!dws->txchan)
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+ goto free_rxchan;
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+ txs = &dw_dma->dmas_tx;
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+ txs->hs_mode = LNW_DMA_HW_HS;
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+ txs->cfg_mode = LNW_DMA_MEM_TO_PER;
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+ dws->txchan->private = txs;
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+
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+ dws->dma_inited = 1;
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+ return 0;
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+
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+free_rxchan:
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+ dma_release_channel(dws->rxchan);
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+err_exit:
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+ return -1;
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+
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+}
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+
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+static void mid_spi_dma_exit(struct dw_spi *dws)
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+{
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+ dma_release_channel(dws->txchan);
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+ dma_release_channel(dws->rxchan);
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+}
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+
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+/*
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+ * dws->dma_chan_done is cleared before the dma transfer starts,
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+ * callback for rx/tx channel will each increment it by 1.
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+ * Reaching 2 means the whole spi transaction is done.
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+ */
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+static void dw_spi_dma_done(void *arg)
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+{
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+ struct dw_spi *dws = arg;
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+
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+ if (++dws->dma_chan_done != 2)
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+ return;
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+ dw_spi_xfer_done(dws);
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+}
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+
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+static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
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+{
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+ struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
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+ struct dma_chan *txchan, *rxchan;
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+ struct dma_slave_config txconf, rxconf;
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+ u16 dma_ctrl = 0;
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+
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+ /* 1. setup DMA related registers */
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+ if (cs_change) {
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+ spi_enable_chip(dws, 0);
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+ dw_writew(dws, dmardlr, 0xf);
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+ dw_writew(dws, dmatdlr, 0x10);
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+ if (dws->tx_dma)
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+ dma_ctrl |= 0x2;
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+ if (dws->rx_dma)
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+ dma_ctrl |= 0x1;
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+ dw_writew(dws, dmacr, dma_ctrl);
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+ spi_enable_chip(dws, 1);
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+ }
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+
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+ dws->dma_chan_done = 0;
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+ txchan = dws->txchan;
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+ rxchan = dws->rxchan;
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+
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+ /* 2. Prepare the TX dma transfer */
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+ txconf.direction = DMA_TO_DEVICE;
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+ txconf.dst_addr = dws->dma_addr;
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+ txconf.dst_maxburst = LNW_DMA_MSIZE_16;
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+ txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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+ txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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+
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+ txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
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+ (unsigned long) &txconf);
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+
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+ memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
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+ dws->tx_sgl.dma_address = dws->tx_dma;
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+ dws->tx_sgl.length = dws->len;
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+
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+ txdesc = txchan->device->device_prep_slave_sg(txchan,
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+ &dws->tx_sgl,
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+ 1,
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+ DMA_TO_DEVICE,
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+ DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
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+ txdesc->callback = dw_spi_dma_done;
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+ txdesc->callback_param = dws;
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+
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+ /* 3. Prepare the RX dma transfer */
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+ rxconf.direction = DMA_FROM_DEVICE;
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+ rxconf.src_addr = dws->dma_addr;
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+ rxconf.src_maxburst = LNW_DMA_MSIZE_16;
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+ rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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+ rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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+
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+ rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
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+ (unsigned long) &rxconf);
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+
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+ memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
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+ dws->rx_sgl.dma_address = dws->rx_dma;
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+ dws->rx_sgl.length = dws->len;
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+
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+ rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
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+ &dws->rx_sgl,
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+ 1,
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+ DMA_FROM_DEVICE,
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+ DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
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+ rxdesc->callback = dw_spi_dma_done;
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+ rxdesc->callback_param = dws;
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+
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+ /* rx must be started before tx due to spi instinct */
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+ rxdesc->tx_submit(rxdesc);
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+ txdesc->tx_submit(txdesc);
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+ return 0;
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+}
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+
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+static struct dw_spi_dma_ops mid_dma_ops = {
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+ .dma_init = mid_spi_dma_init,
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+ .dma_exit = mid_spi_dma_exit,
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+ .dma_transfer = mid_spi_dma_transfer,
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+};
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+#endif
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+
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+/* Some specific info for SPI0 controller on Moorestown */
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+
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+/* HW info for MRST CLk Control Unit, one 32b reg */
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+#define MRST_SPI_CLK_BASE 100000000 /* 100m */
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+#define MRST_CLK_SPI0_REG 0xff11d86c
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+#define CLK_SPI_BDIV_OFFSET 0
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+#define CLK_SPI_BDIV_MASK 0x00000007
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+#define CLK_SPI_CDIV_OFFSET 9
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+#define CLK_SPI_CDIV_MASK 0x00000e00
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+#define CLK_SPI_DISABLE_OFFSET 8
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+
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+int dw_spi_mid_init(struct dw_spi *dws)
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+{
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+ u32 *clk_reg, clk_cdiv;
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+
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+ clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
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+ if (!clk_reg)
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+ return -ENOMEM;
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+
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+ /* get SPI controller operating freq info */
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+ clk_cdiv = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
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+ dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
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+ iounmap(clk_reg);
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+
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+ dws->num_cs = 16;
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+ dws->fifo_len = 40; /* FIFO has 40 words buffer */
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+
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+#ifdef CONFIG_SPI_DW_MID_DMA
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+ dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
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+ if (!dws->dma_priv)
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+ return -ENOMEM;
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+ dws->dma_ops = &mid_dma_ops;
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+#endif
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+ return 0;
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+}
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Feng Tang