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@@ -5168,8 +5168,7 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
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return 120000;
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}
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-static void ironlake_set_pipeconf(struct drm_crtc *crtc,
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- struct drm_display_mode *adjusted_mode)
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+static void ironlake_set_pipeconf(struct drm_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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@@ -5202,7 +5201,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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val &= ~PIPECONF_INTERLACE_MASK;
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- if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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+ if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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val |= PIPECONF_INTERLACED_ILK;
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else
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val |= PIPECONF_PROGRESSIVE;
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@@ -5280,8 +5279,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
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}
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}
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-static void haswell_set_pipeconf(struct drm_crtc *crtc,
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- struct drm_display_mode *adjusted_mode)
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+static void haswell_set_pipeconf(struct drm_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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@@ -5295,7 +5293,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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val &= ~PIPECONF_INTERLACE_MASK_HSW;
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- if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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+ if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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val |= PIPECONF_INTERLACED_ILK;
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else
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val |= PIPECONF_PROGRESSIVE;
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@@ -5753,7 +5751,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
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- ironlake_set_pipeconf(crtc, adjusted_mode);
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+ ironlake_set_pipeconf(crtc);
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/* Set up the display plane register */
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I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
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@@ -5877,7 +5875,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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if (intel_crtc->config.has_pch_encoder)
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ironlake_fdi_set_m_n(crtc);
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- haswell_set_pipeconf(crtc, adjusted_mode);
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+ haswell_set_pipeconf(crtc);
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intel_set_pipe_csc(crtc);
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