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@@ -10,6 +10,22 @@
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#define CPUID_TLBTYPE 3
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#define CPUID_MPIDR 5
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+#ifdef CONFIG_CPU_V7M
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+#define CPUID_EXT_PFR0 0x40
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+#define CPUID_EXT_PFR1 0x44
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+#define CPUID_EXT_DFR0 0x48
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+#define CPUID_EXT_AFR0 0x4c
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+#define CPUID_EXT_MMFR0 0x50
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+#define CPUID_EXT_MMFR1 0x54
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+#define CPUID_EXT_MMFR2 0x58
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+#define CPUID_EXT_MMFR3 0x5c
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+#define CPUID_EXT_ISAR0 0x60
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+#define CPUID_EXT_ISAR1 0x64
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+#define CPUID_EXT_ISAR2 0x68
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+#define CPUID_EXT_ISAR3 0x6c
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+#define CPUID_EXT_ISAR4 0x70
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+#define CPUID_EXT_ISAR5 0x74
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+#else
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#define CPUID_EXT_PFR0 "c1, 0"
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#define CPUID_EXT_PFR1 "c1, 1"
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#define CPUID_EXT_DFR0 "c1, 2"
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@@ -24,6 +40,7 @@
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#define CPUID_EXT_ISAR3 "c2, 3"
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#define CPUID_EXT_ISAR4 "c2, 4"
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#define CPUID_EXT_ISAR5 "c2, 5"
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+#endif
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#define MPIDR_SMP_BITMASK (0x3 << 30)
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#define MPIDR_SMP_VALUE (0x2 << 30)
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@@ -79,7 +96,23 @@ extern unsigned int processor_id;
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__val; \
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})
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-#else /* ifdef CONFIG_CPU_CP15 */
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+#elif defined(CONFIG_CPU_V7M)
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+
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+#include <asm/io.h>
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+#include <asm/v7m.h>
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+
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+#define read_cpuid(reg) \
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+ ({ \
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+ WARN_ON_ONCE(1); \
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+ 0; \
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+ })
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+
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+static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
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+{
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+ return readl(BASEADDR_V7M_SCB + offset);
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+}
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+
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+#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
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/*
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* read_cpuid and read_cpuid_ext should only ever be called on machines that
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@@ -108,9 +141,6 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
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#elif defined(CONFIG_CPU_V7M)
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-#include <asm/io.h>
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-#include <asm/v7m.h>
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-
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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{
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return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
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