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@@ -50,7 +50,7 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
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{
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struct omap_vp_instance *vp = voltdm->vp;
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struct omap_vdd_info *vdd = voltdm->vdd;
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- u32 vp_val;
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+ u32 vp_val, sys_clk_rate, timeout_val, waittime;
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if (!voltdm->read || !voltdm->write) {
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pr_err("%s: No read/write API for accessing vdd_%s regs\n",
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@@ -58,6 +58,27 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
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return;
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}
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+ vp->enabled = false;
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+
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+ /* Divide to avoid overflow */
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+ sys_clk_rate = voltdm->sys_clk.rate / 1000;
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+
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+ vdd->vp_rt_data.vpconfig_erroroffset =
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+ (voltdm->pmic->vp_erroroffset <<
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+ __ffs(voltdm->vp->common->vpconfig_erroroffset_mask));
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+
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+ timeout_val = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
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+ vdd->vp_rt_data.vlimitto_timeout = timeout_val;
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+ vdd->vp_rt_data.vlimitto_vddmin = voltdm->pmic->vp_vddmin;
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+ vdd->vp_rt_data.vlimitto_vddmax = voltdm->pmic->vp_vddmax;
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+
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+ waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
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+ sys_clk_rate) / 1000;
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+ vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
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+ vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
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+ vdd->vp_rt_data.vstepmin_stepmin = voltdm->pmic->vp_vstepmin;
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+ vdd->vp_rt_data.vstepmax_stepmax = voltdm->pmic->vp_vstepmax;
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+
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vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
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(vdd->vp_rt_data.vpconfig_errorgain <<
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__ffs(vp->common->vpconfig_errorgain_mask)) |
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