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@@ -27,6 +27,7 @@
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#include <linux/clockchips.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/module.h>
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+#include <linux/dmar.h>
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#include <asm/atomic.h>
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#include <asm/smp.h>
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@@ -39,6 +40,7 @@
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#include <asm/proto.h>
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#include <asm/timex.h>
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#include <asm/apic.h>
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+#include <asm/i8259.h>
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#include <mach_ipi.h>
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#include <mach_apic.h>
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@@ -46,8 +48,12 @@
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static int disable_apic_timer __cpuinitdata;
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static int apic_calibrate_pmtmr __initdata;
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int disable_apic;
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+int disable_x2apic;
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int x2apic;
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+/* x2apic enabled before OS handover */
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+int x2apic_preenabled;
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+
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/* Local APIC timer works in C2 */
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int local_apic_timer_c2_ok;
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EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
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@@ -896,6 +902,125 @@ void __cpuinit end_local_APIC_setup(void)
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apic_pm_activate();
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}
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+void check_x2apic(void)
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+{
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+ int msr, msr2;
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+
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+ rdmsr(MSR_IA32_APICBASE, msr, msr2);
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+
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+ if (msr & X2APIC_ENABLE) {
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+ printk("x2apic enabled by BIOS, switching to x2apic ops\n");
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+ x2apic_preenabled = x2apic = 1;
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+ apic_ops = &x2apic_ops;
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+ }
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+}
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+
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+void enable_x2apic(void)
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+{
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+ int msr, msr2;
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+
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+ rdmsr(MSR_IA32_APICBASE, msr, msr2);
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+ if (!(msr & X2APIC_ENABLE)) {
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+ printk("Enabling x2apic\n");
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+ wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
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+ }
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+}
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+
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+void enable_IR_x2apic(void)
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+{
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+#ifdef CONFIG_INTR_REMAP
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+ int ret;
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+ unsigned long flags;
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+
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+ if (!cpu_has_x2apic)
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+ return;
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+
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+ if (!x2apic_preenabled && disable_x2apic) {
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+ printk(KERN_INFO
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+ "Skipped enabling x2apic and Interrupt-remapping "
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+ "because of nox2apic\n");
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+ return;
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+ }
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+
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+ if (x2apic_preenabled && disable_x2apic)
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+ panic("Bios already enabled x2apic, can't enforce nox2apic");
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+
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+ if (!x2apic_preenabled && skip_ioapic_setup) {
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+ printk(KERN_INFO
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+ "Skipped enabling x2apic and Interrupt-remapping "
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+ "because of skipping io-apic setup\n");
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+ return;
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+ }
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+
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+ ret = dmar_table_init();
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+ if (ret) {
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+ printk(KERN_INFO
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+ "dmar_table_init() failed with %d:\n", ret);
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+
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+ if (x2apic_preenabled)
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+ panic("x2apic enabled by bios. But IR enabling failed");
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+ else
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+ printk(KERN_INFO
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+ "Not enabling x2apic,Intr-remapping\n");
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+ return;
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+ }
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+
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+ local_irq_save(flags);
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+ mask_8259A();
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+ save_mask_IO_APIC_setup();
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+
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+ ret = enable_intr_remapping(1);
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+
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+ if (ret && x2apic_preenabled) {
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+ local_irq_restore(flags);
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+ panic("x2apic enabled by bios. But IR enabling failed");
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+ }
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+
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+ if (ret)
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+ goto end;
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+
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+ if (!x2apic) {
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+ x2apic = 1;
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+ apic_ops = &x2apic_ops;
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+ enable_x2apic();
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+ }
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+end:
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+ if (ret)
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+ /*
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+ * IR enabling failed
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+ */
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+ restore_IO_APIC_setup();
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+ else
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+ reinit_intr_remapped_IO_APIC(x2apic_preenabled);
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+
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+ unmask_8259A();
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+ local_irq_restore(flags);
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+
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+ if (!ret) {
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+ if (!x2apic_preenabled)
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+ printk(KERN_INFO
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+ "Enabled x2apic and interrupt-remapping\n");
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+ else
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+ printk(KERN_INFO
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+ "Enabled Interrupt-remapping\n");
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+ } else
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+ printk(KERN_ERR
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+ "Failed to enable Interrupt-remapping and x2apic\n");
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+#else
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+ if (!cpu_has_x2apic)
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+ return;
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+
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+ if (x2apic_preenabled)
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+ panic("x2apic enabled prior OS handover,"
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+ " enable CONFIG_INTR_REMAP");
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+
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+ printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
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+ " and x2apic\n");
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+#endif
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+
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+ return;
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+}
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+
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/*
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* Detect and enable local APICs on non-SMP boards.
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* Original code written by Keir Fraser.
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@@ -943,6 +1068,11 @@ void __init early_init_lapic_mapping(void)
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*/
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void __init init_apic_mappings(void)
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{
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+ if (x2apic) {
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+ boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
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+ return;
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+ }
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+
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/*
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* If no local APIC can be found then set up a fake all
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* zeroes page to simulate the local APIC and another
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@@ -981,6 +1111,9 @@ int __init APIC_init_uniprocessor(void)
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return -1;
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}
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+ enable_IR_x2apic();
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+ setup_apic_routing();
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+
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verify_local_APIC();
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connect_bsp_APIC();
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@@ -1238,10 +1371,14 @@ static int lapic_resume(struct sys_device *dev)
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maxlvt = lapic_get_maxlvt();
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local_irq_save(flags);
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- rdmsr(MSR_IA32_APICBASE, l, h);
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- l &= ~MSR_IA32_APICBASE_BASE;
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- l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
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- wrmsr(MSR_IA32_APICBASE, l, h);
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+ if (!x2apic) {
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+ rdmsr(MSR_IA32_APICBASE, l, h);
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+ l &= ~MSR_IA32_APICBASE_BASE;
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+ l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
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+ wrmsr(MSR_IA32_APICBASE, l, h);
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+ } else
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+ enable_x2apic();
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+
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apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
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apic_write(APIC_ID, apic_pm_state.apic_id);
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apic_write(APIC_DFR, apic_pm_state.apic_dfr);
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@@ -1381,6 +1518,15 @@ __cpuinit int apic_is_clustered_box(void)
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return (clusters > 2);
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}
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+static __init int setup_nox2apic(char *str)
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+{
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+ disable_x2apic = 1;
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+ clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
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+ return 0;
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+}
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+early_param("nox2apic", setup_nox2apic);
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+
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+
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/*
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* APIC command line parameters
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*/
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