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@@ -191,6 +191,34 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = {
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{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
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};
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+static u64 __initdata fam10h_mmconf_start;
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+static u64 __initdata fam10h_mmconf_end;
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+static void __init get_pci_mmcfg_amd_fam10h_range(void)
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+{
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+ u32 address;
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+ u64 base, msr;
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+ unsigned segn_busn_bits;
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+
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+ /* assume all cpus from fam10h have mmconf */
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+ if (boot_cpu_data.x86 < 0x10)
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+ return;
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+
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+ address = MSR_FAM10H_MMIO_CONF_BASE;
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+ rdmsrl(address, msr);
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+
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+ /* mmconfig is not enable */
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+ if (!(msr & FAM10H_MMIO_CONF_ENABLE))
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+ return;
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+
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+ base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
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+
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+ segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
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+ FAM10H_MMIO_CONF_BUSRANGE_MASK;
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+
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+ fam10h_mmconf_start = base;
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+ fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
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+}
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+
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/**
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* early_fill_mp_bus_to_node()
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* called before pcibios_scan_root and pci_scan_bus
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@@ -305,6 +333,8 @@ static int __init early_fill_mp_bus_info(void)
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continue; /* not found */
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info = &pci_root_info[j];
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+ printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
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+ node, link, (u64)start, (u64)end);
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update_res(info, start, end, IORESOURCE_IO, 0);
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update_range(range, start, end);
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}
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@@ -328,8 +358,7 @@ static int __init early_fill_mp_bus_info(void)
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memset(range, 0, sizeof(range));
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/* 0xfd00000000-0xffffffffff for HT */
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- /* 0xfc00000000-0xfcffffffff for Family 10h mmconfig*/
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- range[0].end = 0xfbffffffffULL;
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+ range[0].end = (0xfdULL<<32) - 1;
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/* need to take out [0, TOM) for RAM*/
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address = MSR_K8_TOP_MEM1;
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@@ -339,6 +368,14 @@ static int __init early_fill_mp_bus_info(void)
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if (end < (1ULL<<32))
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update_range(range, 0, end - 1);
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+ /* get mmconfig */
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+ get_pci_mmcfg_amd_fam10h_range();
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+ /* need to take out mmconf range */
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+ if (fam10h_mmconf_end) {
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+ printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
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+ update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
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+ }
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+
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/* mmio resource */
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for (i = 0; i < 8; i++) {
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reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
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@@ -364,8 +401,51 @@ static int __init early_fill_mp_bus_info(void)
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continue; /* not found */
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info = &pci_root_info[j];
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+
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+ printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
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+ node, link, (u64)start, (u64)end);
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+ /*
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+ * some sick allocation would have range overlap with fam10h
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+ * mmconf range, so need to update start and end.
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+ */
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+ if (fam10h_mmconf_end) {
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+ int changed = 0;
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+ u64 endx = 0;
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+ if (start >= fam10h_mmconf_start &&
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+ start <= fam10h_mmconf_end) {
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+ start = fam10h_mmconf_end + 1;
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+ changed = 1;
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+ }
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+
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+ if (end >= fam10h_mmconf_start &&
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+ end <= fam10h_mmconf_end) {
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+ end = fam10h_mmconf_start - 1;
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+ changed = 1;
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+ }
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+
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+ if (start < fam10h_mmconf_start &&
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+ end > fam10h_mmconf_end) {
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+ /* we got a hole */
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+ endx = fam10h_mmconf_start - 1;
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+ update_res(info, start, endx, IORESOURCE_MEM, 0);
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+ update_range(range, start, endx);
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+ printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
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+ start = fam10h_mmconf_end + 1;
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+ changed = 1;
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+ }
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+ if (changed) {
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+ if (start <= end) {
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+ printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
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+ } else {
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+ printk(KERN_CONT "%s\n", endx?"":" ==> none");
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+ continue;
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+ }
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+ }
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+ }
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+
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update_res(info, start, end, IORESOURCE_MEM, 0);
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update_range(range, start, end);
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+ printk(KERN_CONT "\n");
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}
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/* need to take out [4G, TOM2) for RAM*/
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