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@@ -17,6 +17,7 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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+#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/pci.h>
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@@ -676,6 +677,104 @@ unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned lon
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EXPORT_SYMBOL(eeh_check_failure);
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+/* ------------------------------------------------------------- */
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+/* The code below deals with error recovery */
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+
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+/** Return negative value if a permanent error, else return
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+ * a number of milliseconds to wait until the PCI slot is
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+ * ready to be used.
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+ */
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+static int
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+eeh_slot_availability(struct pci_dn *pdn)
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+{
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+ int rc;
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+ int rets[3];
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+
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+ rc = read_slot_reset_state(pdn, rets);
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+
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+ if (rc) return rc;
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+
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+ if (rets[1] == 0) return -1; /* EEH is not supported */
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+ if (rets[0] == 0) return 0; /* Oll Korrect */
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+ if (rets[0] == 5) {
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+ if (rets[2] == 0) return -1; /* permanently unavailable */
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+ return rets[2]; /* number of millisecs to wait */
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+ }
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+ return -1;
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+}
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+
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+/** rtas_pci_slot_reset raises/lowers the pci #RST line
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+ * state: 1/0 to raise/lower the #RST
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+ *
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+ * Clear the EEH-frozen condition on a slot. This routine
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+ * asserts the PCI #RST line if the 'state' argument is '1',
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+ * and drops the #RST line if 'state is '0'. This routine is
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+ * safe to call in an interrupt context.
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+ *
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+ */
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+
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+static void
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+rtas_pci_slot_reset(struct pci_dn *pdn, int state)
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+{
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+ int rc;
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+
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+ BUG_ON (pdn==NULL);
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+
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+ if (!pdn->phb) {
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+ printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n",
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+ pdn->node->full_name);
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+ return;
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+ }
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+
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+ rc = rtas_call(ibm_set_slot_reset,4,1, NULL,
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+ pdn->eeh_config_addr,
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+ BUID_HI(pdn->phb->buid),
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+ BUID_LO(pdn->phb->buid),
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+ state);
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+ if (rc) {
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+ printk (KERN_WARNING "EEH: Unable to reset the failed slot, (%d) #RST=%d dn=%s\n",
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+ rc, state, pdn->node->full_name);
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+ return;
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+ }
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+
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+ if (state == 0)
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+ eeh_clear_slot (pdn->node->parent->child);
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+}
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+
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+/** rtas_set_slot_reset -- assert the pci #RST line for 1/4 second
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+ * dn -- device node to be reset.
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+ */
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+
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+void
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+rtas_set_slot_reset(struct pci_dn *pdn)
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+{
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+ int i, rc;
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+
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+ rtas_pci_slot_reset (pdn, 1);
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+
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+ /* The PCI bus requires that the reset be held high for at least
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+ * a 100 milliseconds. We wait a bit longer 'just in case'. */
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+
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+#define PCI_BUS_RST_HOLD_TIME_MSEC 250
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+ msleep (PCI_BUS_RST_HOLD_TIME_MSEC);
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+ rtas_pci_slot_reset (pdn, 0);
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+
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+ /* After a PCI slot has been reset, the PCI Express spec requires
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+ * a 1.5 second idle time for the bus to stabilize, before starting
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+ * up traffic. */
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+#define PCI_BUS_SETTLE_TIME_MSEC 1800
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+ msleep (PCI_BUS_SETTLE_TIME_MSEC);
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+
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+ /* Now double check with the firmware to make sure the device is
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+ * ready to be used; if not, wait for recovery. */
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+ for (i=0; i<10; i++) {
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+ rc = eeh_slot_availability (pdn);
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+ if (rc <= 0) break;
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+
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+ msleep (rc+100);
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+ }
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+}
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+
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/* ------------------------------------------------------------- */
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/* The code below deals with enabling EEH for devices during the
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* early boot sequence. EEH must be enabled before any PCI probing
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