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@@ -447,10 +447,10 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
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* It invalidates a single PTE if the range to flush is within a single
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* page. Otherwise it flushes the whole TLB of the IOMMU.
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*/
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-static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
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- u64 address, size_t size)
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+static void __iommu_flush_pages(struct protection_domain *domain,
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+ u64 address, size_t size, int pde)
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{
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- int s = 0;
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+ int s = 0, i;
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unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
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address &= PAGE_MASK;
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@@ -464,9 +464,26 @@ static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
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s = 1;
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}
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- iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
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- return 0;
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+ for (i = 0; i < amd_iommus_present; ++i) {
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+ if (!domain->dev_iommu[i])
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+ continue;
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+
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+ /*
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+ * Devices of this domain are behind this IOMMU
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+ * We need a TLB flush
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+ */
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+ iommu_queue_inv_iommu_pages(amd_iommus[i], address,
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+ domain->id, pde, s);
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+ }
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+
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+ return;
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+}
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+
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+static void iommu_flush_pages(struct protection_domain *domain,
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+ u64 address, size_t size)
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+{
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+ __iommu_flush_pages(domain, address, size, 0);
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}
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/* Flush the whole IO/TLB for a given protection domain */
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@@ -1683,7 +1700,7 @@ retry:
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iommu_flush_tlb(iommu, dma_dom->domain.id);
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dma_dom->need_flush = false;
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} else if (unlikely(iommu_has_npcache(iommu)))
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- iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
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+ iommu_flush_pages(&dma_dom->domain, address, size);
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out:
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return address;
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@@ -1731,7 +1748,7 @@ static void __unmap_single(struct amd_iommu *iommu,
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dma_ops_free_addresses(dma_dom, dma_addr, pages);
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if (amd_iommu_unmap_flush || dma_dom->need_flush) {
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- iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
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+ iommu_flush_pages(&dma_dom->domain, dma_addr, size);
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dma_dom->need_flush = false;
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}
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}
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