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@@ -266,6 +266,33 @@ static const unsigned crb_hub_agt[64] = {
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0,
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};
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+static void qlcnic_read_dump_reg(u32 addr, void __iomem *bar0, u32 *data)
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+{
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+ u32 dest;
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+ void __iomem *window_reg;
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+
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+ dest = addr & 0xFFFF0000;
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+ window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
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+ writel(dest, window_reg);
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+ readl(window_reg);
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+ window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
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+ *data = readl(window_reg);
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+}
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+
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+static void qlcnic_write_dump_reg(u32 addr, void __iomem *bar0, u32 data)
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+{
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+ u32 dest;
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+ void __iomem *window_reg;
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+
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+ dest = addr & 0xFFFF0000;
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+ window_reg = bar0 + QLCNIC_FW_DUMP_REG1;
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+ writel(dest, window_reg);
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+ readl(window_reg);
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+ window_reg = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
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+ writel(data, window_reg);
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+ readl(window_reg);
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+}
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+
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/* PCI Windowing for DDR regions. */
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#define QLCNIC_PCIE_SEM_TIMEOUT 10000
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@@ -540,7 +567,7 @@ void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
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}
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}
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-int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
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+static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
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{
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struct qlcnic_nic_req req;
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int rv;
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@@ -1334,7 +1361,7 @@ qlcnic_dump_crb(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
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addr = crb->addr;
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for (i = 0; i < crb->no_ops; i++) {
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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+ qlcnic_read_dump_reg(addr, base, &data);
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*buffer++ = cpu_to_le32(addr);
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*buffer++ = cpu_to_le32(data);
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addr += crb->stride;
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@@ -1364,25 +1391,25 @@ qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
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continue;
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switch (1 << k) {
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case QLCNIC_DUMP_WCRB:
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- QLCNIC_WR_DUMP_REG(addr, base, ctr->val1);
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+ qlcnic_write_dump_reg(addr, base, ctr->val1);
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break;
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case QLCNIC_DUMP_RWCRB:
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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- QLCNIC_WR_DUMP_REG(addr, base, data);
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+ qlcnic_read_dump_reg(addr, base, &data);
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+ qlcnic_write_dump_reg(addr, base, data);
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break;
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case QLCNIC_DUMP_ANDCRB:
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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- QLCNIC_WR_DUMP_REG(addr, base,
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- (data & ctr->val2));
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+ qlcnic_read_dump_reg(addr, base, &data);
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+ qlcnic_write_dump_reg(addr, base,
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+ data & ctr->val2);
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break;
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case QLCNIC_DUMP_ORCRB:
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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- QLCNIC_WR_DUMP_REG(addr, base,
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- (data | ctr->val3));
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+ qlcnic_read_dump_reg(addr, base, &data);
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+ qlcnic_write_dump_reg(addr, base,
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+ data | ctr->val3);
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break;
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case QLCNIC_DUMP_POLLCRB:
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while (timeout <= ctr->timeout) {
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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+ qlcnic_read_dump_reg(addr, base, &data);
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if ((data & ctr->val2) == ctr->val1)
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break;
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msleep(1);
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@@ -1397,7 +1424,7 @@ qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
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case QLCNIC_DUMP_RD_SAVE:
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if (ctr->index_a)
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addr = t_hdr->saved_state[ctr->index_a];
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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+ qlcnic_read_dump_reg(addr, base, &data);
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t_hdr->saved_state[ctr->index_v] = data;
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break;
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case QLCNIC_DUMP_WRT_SAVED:
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@@ -1407,7 +1434,7 @@ qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
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data = ctr->val1;
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if (ctr->index_a)
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addr = t_hdr->saved_state[ctr->index_a];
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- QLCNIC_WR_DUMP_REG(addr, base, data);
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+ qlcnic_write_dump_reg(addr, base, data);
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break;
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case QLCNIC_DUMP_MOD_SAVE_ST:
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data = t_hdr->saved_state[ctr->index_v];
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@@ -1441,8 +1468,8 @@ qlcnic_dump_mux(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
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val = mux->val;
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for (loop = 0; loop < mux->no_ops; loop++) {
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- QLCNIC_WR_DUMP_REG(mux->addr, base, val);
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- QLCNIC_RD_DUMP_REG(mux->read_addr, base, &data);
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+ qlcnic_write_dump_reg(mux->addr, base, val);
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+ qlcnic_read_dump_reg(mux->read_addr, base, &data);
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*buffer++ = cpu_to_le32(val);
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*buffer++ = cpu_to_le32(data);
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val += mux->val_stride;
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@@ -1463,10 +1490,10 @@ qlcnic_dump_que(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
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cnt = que->read_addr_cnt;
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for (loop = 0; loop < que->no_ops; loop++) {
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- QLCNIC_WR_DUMP_REG(que->sel_addr, base, que_id);
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+ qlcnic_write_dump_reg(que->sel_addr, base, que_id);
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addr = que->read_addr;
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for (i = 0; i < cnt; i++) {
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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+ qlcnic_read_dump_reg(addr, base, &data);
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*buffer++ = cpu_to_le32(data);
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addr += que->read_addr_stride;
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}
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@@ -1514,9 +1541,9 @@ lock_try:
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writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
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for (i = 0; i < size; i++) {
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addr = fl_addr & 0xFFFF0000;
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- QLCNIC_WR_DUMP_REG(FLASH_ROM_WINDOW, base, addr);
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+ qlcnic_write_dump_reg(FLASH_ROM_WINDOW, base, addr);
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addr = LSW(fl_addr) + FLASH_ROM_DATA;
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- QLCNIC_RD_DUMP_REG(addr, base, &val);
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+ qlcnic_read_dump_reg(addr, base, &val);
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fl_addr += 4;
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*buffer++ = cpu_to_le32(val);
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}
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@@ -1536,12 +1563,12 @@ qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
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val = l1->init_tag_val;
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for (i = 0; i < l1->no_ops; i++) {
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- QLCNIC_WR_DUMP_REG(l1->addr, base, val);
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- QLCNIC_WR_DUMP_REG(l1->ctrl_addr, base, LSW(l1->ctrl_val));
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+ qlcnic_write_dump_reg(l1->addr, base, val);
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+ qlcnic_write_dump_reg(l1->ctrl_addr, base, LSW(l1->ctrl_val));
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addr = l1->read_addr;
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cnt = l1->read_addr_num;
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while (cnt) {
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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+ qlcnic_read_dump_reg(addr, base, &data);
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*buffer++ = cpu_to_le32(data);
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addr += l1->read_addr_stride;
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cnt--;
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@@ -1566,14 +1593,14 @@ qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
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poll_to = MSB(MSW(l2->ctrl_val));
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for (i = 0; i < l2->no_ops; i++) {
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- QLCNIC_WR_DUMP_REG(l2->addr, base, val);
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+ qlcnic_write_dump_reg(l2->addr, base, val);
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if (LSW(l2->ctrl_val))
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- QLCNIC_WR_DUMP_REG(l2->ctrl_addr, base,
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- LSW(l2->ctrl_val));
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+ qlcnic_write_dump_reg(l2->ctrl_addr, base,
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+ LSW(l2->ctrl_val));
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if (!poll_mask)
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goto skip_poll;
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do {
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- QLCNIC_RD_DUMP_REG(l2->ctrl_addr, base, &data);
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+ qlcnic_read_dump_reg(l2->ctrl_addr, base, &data);
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if (!(data & poll_mask))
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break;
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msleep(1);
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@@ -1590,7 +1617,7 @@ skip_poll:
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addr = l2->read_addr;
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cnt = l2->read_addr_num;
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while (cnt) {
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- QLCNIC_RD_DUMP_REG(addr, base, &data);
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+ qlcnic_read_dump_reg(addr, base, &data);
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*buffer++ = cpu_to_le32(data);
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addr += l2->read_addr_stride;
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cnt--;
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@@ -1622,13 +1649,13 @@ qlcnic_read_memory(struct qlcnic_adapter *adapter,
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mutex_lock(&adapter->ahw->mem_lock);
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while (reg_read != 0) {
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- QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_LO, base, addr);
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- QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_HI, base, 0);
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- QLCNIC_WR_DUMP_REG(MIU_TEST_CTR, base,
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- TA_CTL_ENABLE | TA_CTL_START);
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+ qlcnic_write_dump_reg(MIU_TEST_ADDR_LO, base, addr);
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+ qlcnic_write_dump_reg(MIU_TEST_ADDR_HI, base, 0);
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+ qlcnic_write_dump_reg(MIU_TEST_CTR, base,
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+ TA_CTL_ENABLE | TA_CTL_START);
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for (i = 0; i < MAX_CTL_CHECK; i++) {
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- QLCNIC_RD_DUMP_REG(MIU_TEST_CTR, base, &test);
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+ qlcnic_read_dump_reg(MIU_TEST_CTR, base, &test);
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if (!(test & TA_CTL_BUSY))
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break;
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}
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@@ -1641,7 +1668,8 @@ qlcnic_read_memory(struct qlcnic_adapter *adapter,
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}
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}
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for (i = 0; i < 4; i++) {
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- QLCNIC_RD_DUMP_REG(MIU_TEST_READ_DATA[i], base, &data);
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+ qlcnic_read_dump_reg(MIU_TEST_READ_DATA[i], base,
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+ &data);
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*buffer++ = cpu_to_le32(data);
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}
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addr += 16;
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@@ -1661,7 +1689,7 @@ qlcnic_dump_nop(struct qlcnic_adapter *adapter,
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return 0;
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}
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-struct qlcnic_dump_operations fw_dump_ops[] = {
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+static const struct qlcnic_dump_operations fw_dump_ops[] = {
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{ QLCNIC_DUMP_NOP, qlcnic_dump_nop },
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{ QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
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{ QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
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