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@@ -96,6 +96,22 @@ static struct vendor_data vendor_st = {
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};
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/* Deals with DMA transactions */
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+
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+struct pl011_sgbuf {
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+ struct scatterlist sg;
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+ char *buf;
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+};
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+
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+struct pl011_dmarx_data {
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+ struct dma_chan *chan;
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+ struct completion complete;
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+ bool use_buf_b;
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+ struct pl011_sgbuf sgbuf_a;
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+ struct pl011_sgbuf sgbuf_b;
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+ dma_cookie_t cookie;
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+ bool running;
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+};
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+
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struct pl011_dmatx_data {
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struct dma_chan *chan;
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struct scatterlist sg;
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@@ -120,11 +136,69 @@ struct uart_amba_port {
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char type[12];
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#ifdef CONFIG_DMA_ENGINE
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/* DMA stuff */
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- bool using_dma;
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+ bool using_tx_dma;
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+ bool using_rx_dma;
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+ struct pl011_dmarx_data dmarx;
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struct pl011_dmatx_data dmatx;
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#endif
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};
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+/*
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+ * Reads up to 256 characters from the FIFO or until it's empty and
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+ * inserts them into the TTY layer. Returns the number of characters
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+ * read from the FIFO.
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+ */
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+static int pl011_fifo_to_tty(struct uart_amba_port *uap)
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+{
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+ u16 status, ch;
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+ unsigned int flag, max_count = 256;
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+ int fifotaken = 0;
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+
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+ while (max_count--) {
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+ status = readw(uap->port.membase + UART01x_FR);
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+ if (status & UART01x_FR_RXFE)
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+ break;
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+
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+ /* Take chars from the FIFO and update status */
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+ ch = readw(uap->port.membase + UART01x_DR) |
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+ UART_DUMMY_DR_RX;
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+ flag = TTY_NORMAL;
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+ uap->port.icount.rx++;
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+ fifotaken++;
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+
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+ if (unlikely(ch & UART_DR_ERROR)) {
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+ if (ch & UART011_DR_BE) {
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+ ch &= ~(UART011_DR_FE | UART011_DR_PE);
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+ uap->port.icount.brk++;
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+ if (uart_handle_break(&uap->port))
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+ continue;
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+ } else if (ch & UART011_DR_PE)
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+ uap->port.icount.parity++;
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+ else if (ch & UART011_DR_FE)
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+ uap->port.icount.frame++;
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+ if (ch & UART011_DR_OE)
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+ uap->port.icount.overrun++;
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+
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+ ch &= uap->port.read_status_mask;
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+
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+ if (ch & UART011_DR_BE)
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+ flag = TTY_BREAK;
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+ else if (ch & UART011_DR_PE)
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+ flag = TTY_PARITY;
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+ else if (ch & UART011_DR_FE)
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+ flag = TTY_FRAME;
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+ }
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+
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+ if (uart_handle_sysrq_char(&uap->port, ch & 255))
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+ continue;
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+
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+ uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
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+ }
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+
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+ return fifotaken;
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+}
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+
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+
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/*
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* All the DMA operation mode stuff goes inside this ifdef.
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* This assumes that you have a generic DMA device interface,
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@@ -134,6 +208,31 @@ struct uart_amba_port {
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#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
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+static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
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+ enum dma_data_direction dir)
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+{
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+ sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
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+ if (!sg->buf)
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+ return -ENOMEM;
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+
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+ sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
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+
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+ if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
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+ kfree(sg->buf);
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+ return -EINVAL;
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+ }
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+ return 0;
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+}
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+
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+static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
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+ enum dma_data_direction dir)
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+{
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+ if (sg->buf) {
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+ dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
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+ kfree(sg->buf);
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+ }
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+}
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+
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static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
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{
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/* DMA is the sole user of the platform data right now */
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@@ -153,7 +252,7 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
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return;
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}
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- /* Try to acquire a generic DMA engine slave channel */
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+ /* Try to acquire a generic DMA engine slave TX channel */
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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@@ -168,6 +267,28 @@ static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
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dev_info(uap->port.dev, "DMA channel TX %s\n",
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dma_chan_name(uap->dmatx.chan));
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+
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+ /* Optionally make use of an RX channel as well */
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+ if (plat->dma_rx_param) {
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+ struct dma_slave_config rx_conf = {
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+ .src_addr = uap->port.mapbase + UART01x_DR,
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+ .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
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+ .direction = DMA_FROM_DEVICE,
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+ .src_maxburst = uap->fifosize >> 1,
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+ };
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+
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+ chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
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+ if (!chan) {
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+ dev_err(uap->port.dev, "no RX DMA channel!\n");
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+ return;
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+ }
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+
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+ dmaengine_slave_config(chan, &rx_conf);
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+ uap->dmarx.chan = chan;
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+
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+ dev_info(uap->port.dev, "DMA channel RX %s\n",
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+ dma_chan_name(uap->dmarx.chan));
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+ }
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}
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#ifndef MODULE
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@@ -219,9 +340,10 @@ static void pl011_dma_remove(struct uart_amba_port *uap)
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/* TODO: remove the initcall if it has not yet executed */
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if (uap->dmatx.chan)
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dma_release_channel(uap->dmatx.chan);
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+ if (uap->dmarx.chan)
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+ dma_release_channel(uap->dmarx.chan);
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}
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-
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/* Forward declare this for the refill routine */
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static int pl011_dma_tx_refill(struct uart_amba_port *uap);
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@@ -380,7 +502,7 @@ static int pl011_dma_tx_refill(struct uart_amba_port *uap)
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*/
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static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
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{
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- if (!uap->using_dma)
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+ if (!uap->using_tx_dma)
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return false;
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/*
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@@ -432,7 +554,7 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
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{
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u16 dmacr;
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- if (!uap->using_dma)
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+ if (!uap->using_tx_dma)
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return false;
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if (!uap->port.x_char) {
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@@ -492,7 +614,7 @@ static void pl011_dma_flush_buffer(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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- if (!uap->using_dma)
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+ if (!uap->using_tx_dma)
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return;
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/* Avoid deadlock with the DMA engine callback */
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@@ -508,9 +630,219 @@ static void pl011_dma_flush_buffer(struct uart_port *port)
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}
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}
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+static void pl011_dma_rx_callback(void *data);
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+
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+static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
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+{
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+ struct dma_chan *rxchan = uap->dmarx.chan;
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+ struct dma_device *dma_dev;
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+ struct pl011_dmarx_data *dmarx = &uap->dmarx;
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+ struct dma_async_tx_descriptor *desc;
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+ struct pl011_sgbuf *sgbuf;
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+
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+ if (!rxchan)
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+ return -EIO;
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+
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+ /* Start the RX DMA job */
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+ sgbuf = uap->dmarx.use_buf_b ?
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+ &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
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+ dma_dev = rxchan->device;
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+ desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1,
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+ DMA_FROM_DEVICE,
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+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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+ /*
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+ * If the DMA engine is busy and cannot prepare a
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+ * channel, no big deal, the driver will fall back
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+ * to interrupt mode as a result of this error code.
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+ */
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+ if (!desc) {
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+ uap->dmarx.running = false;
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+ dmaengine_terminate_all(rxchan);
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+ return -EBUSY;
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+ }
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+
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+ /* Some data to go along to the callback */
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+ desc->callback = pl011_dma_rx_callback;
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+ desc->callback_param = uap;
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+ dmarx->cookie = dmaengine_submit(desc);
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+ dma_async_issue_pending(rxchan);
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+
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+ uap->dmacr |= UART011_RXDMAE;
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+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ uap->dmarx.running = true;
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+
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+ uap->im &= ~UART011_RXIM;
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+ writew(uap->im, uap->port.membase + UART011_IMSC);
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+
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+ return 0;
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+}
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+
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+/*
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+ * This is called when either the DMA job is complete, or
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+ * the FIFO timeout interrupt occurred. This must be called
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+ * with the port spinlock uap->port.lock held.
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+ */
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+static void pl011_dma_rx_chars(struct uart_amba_port *uap,
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+ u32 pending, bool use_buf_b,
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+ bool readfifo)
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+{
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+ struct tty_struct *tty = uap->port.state->port.tty;
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+ struct pl011_sgbuf *sgbuf = use_buf_b ?
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+ &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
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+ struct device *dev = uap->dmarx.chan->device->dev;
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+ int dma_count = 0;
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+ u32 fifotaken = 0; /* only used for vdbg() */
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+
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+ /* Pick everything from the DMA first */
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+ if (pending) {
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+ /* Sync in buffer */
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+ dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
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+
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+ /*
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+ * First take all chars in the DMA pipe, then look in the FIFO.
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+ * Note that tty_insert_flip_buf() tries to take as many chars
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+ * as it can.
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+ */
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+ dma_count = tty_insert_flip_string(uap->port.state->port.tty,
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+ sgbuf->buf, pending);
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+
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+ /* Return buffer to device */
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+ dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
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+
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+ uap->port.icount.rx += dma_count;
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+ if (dma_count < pending)
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+ dev_warn(uap->port.dev,
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+ "couldn't insert all characters (TTY is full?)\n");
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+ }
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+
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+ /*
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+ * Only continue with trying to read the FIFO if all DMA chars have
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+ * been taken first.
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+ */
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+ if (dma_count == pending && readfifo) {
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+ /* Clear any error flags */
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+ writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
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+ uap->port.membase + UART011_ICR);
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+
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+ /*
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+ * If we read all the DMA'd characters, and we had an
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+ * incomplete buffer, that could be due to an rx error, or
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+ * maybe we just timed out. Read any pending chars and check
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+ * the error status.
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+ *
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+ * Error conditions will only occur in the FIFO, these will
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+ * trigger an immediate interrupt and stop the DMA job, so we
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+ * will always find the error in the FIFO, never in the DMA
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+ * buffer.
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+ */
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+ fifotaken = pl011_fifo_to_tty(uap);
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+ }
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+
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+ spin_unlock(&uap->port.lock);
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+ dev_vdbg(uap->port.dev,
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+ "Took %d chars from DMA buffer and %d chars from the FIFO\n",
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+ dma_count, fifotaken);
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+ tty_flip_buffer_push(tty);
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+ spin_lock(&uap->port.lock);
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+}
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+
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+static void pl011_dma_rx_irq(struct uart_amba_port *uap)
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+{
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+ struct pl011_dmarx_data *dmarx = &uap->dmarx;
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+ struct dma_chan *rxchan = dmarx->chan;
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+ struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
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+ &dmarx->sgbuf_b : &dmarx->sgbuf_a;
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+ size_t pending;
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+ struct dma_tx_state state;
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+ enum dma_status dmastat;
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+
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+ /*
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+ * Pause the transfer so we can trust the current counter,
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+ * do this before we pause the PL011 block, else we may
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+ * overflow the FIFO.
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+ */
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+ if (dmaengine_pause(rxchan))
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+ dev_err(uap->port.dev, "unable to pause DMA transfer\n");
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+ dmastat = rxchan->device->device_tx_status(rxchan,
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+ dmarx->cookie, &state);
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+ if (dmastat != DMA_PAUSED)
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+ dev_err(uap->port.dev, "unable to pause DMA transfer\n");
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+
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+ /* Disable RX DMA - incoming data will wait in the FIFO */
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+ uap->dmacr &= ~UART011_RXDMAE;
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+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ uap->dmarx.running = false;
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+
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+ pending = sgbuf->sg.length - state.residue;
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+ BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
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+ /* Then we terminate the transfer - we now know our residue */
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+ dmaengine_terminate_all(rxchan);
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+
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+ /*
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+ * This will take the chars we have so far and insert
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+ * into the framework.
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+ */
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+ pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
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+
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+ /* Switch buffer & re-trigger DMA job */
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+ dmarx->use_buf_b = !dmarx->use_buf_b;
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+ if (pl011_dma_rx_trigger_dma(uap)) {
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+ dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
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+ "fall back to interrupt mode\n");
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+ uap->im |= UART011_RXIM;
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+ writew(uap->im, uap->port.membase + UART011_IMSC);
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+ }
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+}
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+
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+static void pl011_dma_rx_callback(void *data)
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+{
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+ struct uart_amba_port *uap = data;
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+ struct pl011_dmarx_data *dmarx = &uap->dmarx;
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+ bool lastbuf = dmarx->use_buf_b;
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+ int ret;
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+
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+ /*
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+ * This completion interrupt occurs typically when the
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+ * RX buffer is totally stuffed but no timeout has yet
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+ * occurred. When that happens, we just want the RX
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+ * routine to flush out the secondary DMA buffer while
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+ * we immediately trigger the next DMA job.
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+ */
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+ spin_lock_irq(&uap->port.lock);
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+ uap->dmarx.running = false;
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+ dmarx->use_buf_b = !lastbuf;
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+ ret = pl011_dma_rx_trigger_dma(uap);
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+
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+ pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false);
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+ spin_unlock_irq(&uap->port.lock);
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+ /*
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+ * Do this check after we picked the DMA chars so we don't
|
|
|
+ * get some IRQ immediately from RX.
|
|
|
+ */
|
|
|
+ if (ret) {
|
|
|
+ dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
|
|
|
+ "fall back to interrupt mode\n");
|
|
|
+ uap->im |= UART011_RXIM;
|
|
|
+ writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * Stop accepting received characters, when we're shutting down or
|
|
|
+ * suspending this port.
|
|
|
+ * Locking: called with port lock held and IRQs disabled.
|
|
|
+ */
|
|
|
+static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+ /* FIXME. Just disable the DMA enable */
|
|
|
+ uap->dmacr &= ~UART011_RXDMAE;
|
|
|
+ writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
|
|
+}
|
|
|
|
|
|
static void pl011_dma_startup(struct uart_amba_port *uap)
|
|
|
{
|
|
|
+ int ret;
|
|
|
+
|
|
|
if (!uap->dmatx.chan)
|
|
|
return;
|
|
|
|
|
@@ -525,8 +857,33 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
|
|
|
|
|
|
/* The DMA buffer is now the FIFO the TTY subsystem can use */
|
|
|
uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
|
|
|
- uap->using_dma = true;
|
|
|
+ uap->using_tx_dma = true;
|
|
|
+
|
|
|
+ if (!uap->dmarx.chan)
|
|
|
+ goto skip_rx;
|
|
|
+
|
|
|
+ /* Allocate and map DMA RX buffers */
|
|
|
+ ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
|
|
|
+ DMA_FROM_DEVICE);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
|
|
|
+ "RX buffer A", ret);
|
|
|
+ goto skip_rx;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
|
|
|
+ DMA_FROM_DEVICE);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
|
|
|
+ "RX buffer B", ret);
|
|
|
+ pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
|
|
|
+ DMA_FROM_DEVICE);
|
|
|
+ goto skip_rx;
|
|
|
+ }
|
|
|
|
|
|
+ uap->using_rx_dma = true;
|
|
|
+
|
|
|
+skip_rx:
|
|
|
/* Turn on DMA error (RX/TX will be enabled on demand) */
|
|
|
uap->dmacr |= UART011_DMAONERR;
|
|
|
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
|
@@ -539,11 +896,17 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
|
|
|
if (uap->vendor->dma_threshold)
|
|
|
writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
|
|
|
uap->port.membase + ST_UART011_DMAWM);
|
|
|
+
|
|
|
+ if (uap->using_rx_dma) {
|
|
|
+ if (pl011_dma_rx_trigger_dma(uap))
|
|
|
+ dev_dbg(uap->port.dev, "could not trigger initial "
|
|
|
+ "RX DMA job, fall back to interrupt mode\n");
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
static void pl011_dma_shutdown(struct uart_amba_port *uap)
|
|
|
{
|
|
|
- if (!uap->using_dma)
|
|
|
+ if (!(uap->using_tx_dma || uap->using_rx_dma))
|
|
|
return;
|
|
|
|
|
|
/* Disable RX and TX DMA */
|
|
@@ -555,19 +918,39 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
|
|
|
writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
|
|
spin_unlock_irq(&uap->port.lock);
|
|
|
|
|
|
- /* In theory, this should already be done by pl011_dma_flush_buffer */
|
|
|
- dmaengine_terminate_all(uap->dmatx.chan);
|
|
|
- if (uap->dmatx.queued) {
|
|
|
- dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
|
|
|
- DMA_TO_DEVICE);
|
|
|
- uap->dmatx.queued = false;
|
|
|
+ if (uap->using_tx_dma) {
|
|
|
+ /* In theory, this should already be done by pl011_dma_flush_buffer */
|
|
|
+ dmaengine_terminate_all(uap->dmatx.chan);
|
|
|
+ if (uap->dmatx.queued) {
|
|
|
+ dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
|
|
|
+ DMA_TO_DEVICE);
|
|
|
+ uap->dmatx.queued = false;
|
|
|
+ }
|
|
|
+
|
|
|
+ kfree(uap->dmatx.buf);
|
|
|
+ uap->using_tx_dma = false;
|
|
|
}
|
|
|
|
|
|
- kfree(uap->dmatx.buf);
|
|
|
+ if (uap->using_rx_dma) {
|
|
|
+ dmaengine_terminate_all(uap->dmarx.chan);
|
|
|
+ /* Clean up the RX DMA */
|
|
|
+ pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
|
|
|
+ pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
|
|
|
+ uap->using_rx_dma = false;
|
|
|
+ }
|
|
|
+}
|
|
|
|
|
|
- uap->using_dma = false;
|
|
|
+static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+ return uap->using_rx_dma;
|
|
|
}
|
|
|
|
|
|
+static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+ return uap->using_rx_dma && uap->dmarx.running;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
#else
|
|
|
/* Blank functions if the DMA engine is not available */
|
|
|
static inline void pl011_dma_probe(struct uart_amba_port *uap)
|
|
@@ -600,6 +983,29 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
|
|
|
return false;
|
|
|
}
|
|
|
|
|
|
+static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+}
|
|
|
+
|
|
|
+static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+}
|
|
|
+
|
|
|
+static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+ return -EIO;
|
|
|
+}
|
|
|
+
|
|
|
+static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+ return false;
|
|
|
+}
|
|
|
+
|
|
|
+static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+ return false;
|
|
|
+}
|
|
|
+
|
|
|
#define pl011_dma_flush_buffer NULL
|
|
|
#endif
|
|
|
|
|
@@ -630,6 +1036,8 @@ static void pl011_stop_rx(struct uart_port *port)
|
|
|
uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
|
|
|
UART011_PEIM|UART011_BEIM|UART011_OEIM);
|
|
|
writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+
|
|
|
+ pl011_dma_rx_stop(uap);
|
|
|
}
|
|
|
|
|
|
static void pl011_enable_ms(struct uart_port *port)
|
|
@@ -643,51 +1051,24 @@ static void pl011_enable_ms(struct uart_port *port)
|
|
|
static void pl011_rx_chars(struct uart_amba_port *uap)
|
|
|
{
|
|
|
struct tty_struct *tty = uap->port.state->port.tty;
|
|
|
- unsigned int status, ch, flag, max_count = 256;
|
|
|
-
|
|
|
- status = readw(uap->port.membase + UART01x_FR);
|
|
|
- while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
|
|
|
- ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
|
|
|
- flag = TTY_NORMAL;
|
|
|
- uap->port.icount.rx++;
|
|
|
-
|
|
|
- /*
|
|
|
- * Note that the error handling code is
|
|
|
- * out of the main execution path
|
|
|
- */
|
|
|
- if (unlikely(ch & UART_DR_ERROR)) {
|
|
|
- if (ch & UART011_DR_BE) {
|
|
|
- ch &= ~(UART011_DR_FE | UART011_DR_PE);
|
|
|
- uap->port.icount.brk++;
|
|
|
- if (uart_handle_break(&uap->port))
|
|
|
- goto ignore_char;
|
|
|
- } else if (ch & UART011_DR_PE)
|
|
|
- uap->port.icount.parity++;
|
|
|
- else if (ch & UART011_DR_FE)
|
|
|
- uap->port.icount.frame++;
|
|
|
- if (ch & UART011_DR_OE)
|
|
|
- uap->port.icount.overrun++;
|
|
|
-
|
|
|
- ch &= uap->port.read_status_mask;
|
|
|
-
|
|
|
- if (ch & UART011_DR_BE)
|
|
|
- flag = TTY_BREAK;
|
|
|
- else if (ch & UART011_DR_PE)
|
|
|
- flag = TTY_PARITY;
|
|
|
- else if (ch & UART011_DR_FE)
|
|
|
- flag = TTY_FRAME;
|
|
|
- }
|
|
|
|
|
|
- if (uart_handle_sysrq_char(&uap->port, ch & 255))
|
|
|
- goto ignore_char;
|
|
|
-
|
|
|
- uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
|
|
|
+ pl011_fifo_to_tty(uap);
|
|
|
|
|
|
- ignore_char:
|
|
|
- status = readw(uap->port.membase + UART01x_FR);
|
|
|
- }
|
|
|
spin_unlock(&uap->port.lock);
|
|
|
tty_flip_buffer_push(tty);
|
|
|
+ /*
|
|
|
+ * If we were temporarily out of DMA mode for a while,
|
|
|
+ * attempt to switch back to DMA mode again.
|
|
|
+ */
|
|
|
+ if (pl011_dma_rx_available(uap)) {
|
|
|
+ if (pl011_dma_rx_trigger_dma(uap)) {
|
|
|
+ dev_dbg(uap->port.dev, "could not trigger RX DMA job "
|
|
|
+ "fall back to interrupt mode again\n");
|
|
|
+ uap->im |= UART011_RXIM;
|
|
|
+ } else
|
|
|
+ uap->im &= ~UART011_RXIM;
|
|
|
+ writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ }
|
|
|
spin_lock(&uap->port.lock);
|
|
|
}
|
|
|
|
|
@@ -767,8 +1148,12 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
|
|
|
UART011_RXIS),
|
|
|
uap->port.membase + UART011_ICR);
|
|
|
|
|
|
- if (status & (UART011_RTIS|UART011_RXIS))
|
|
|
- pl011_rx_chars(uap);
|
|
|
+ if (status & (UART011_RTIS|UART011_RXIS)) {
|
|
|
+ if (pl011_dma_rx_running(uap))
|
|
|
+ pl011_dma_rx_irq(uap);
|
|
|
+ else
|
|
|
+ pl011_rx_chars(uap);
|
|
|
+ }
|
|
|
if (status & (UART011_DSRMIS|UART011_DCDMIS|
|
|
|
UART011_CTSMIS|UART011_RIMIS))
|
|
|
pl011_modem_status(uap);
|
|
@@ -945,10 +1330,14 @@ static int pl011_startup(struct uart_port *port)
|
|
|
pl011_dma_startup(uap);
|
|
|
|
|
|
/*
|
|
|
- * Finally, enable interrupts
|
|
|
+ * Finally, enable interrupts, only timeouts when using DMA
|
|
|
+ * if initial RX DMA job failed, start in interrupt mode
|
|
|
+ * as well.
|
|
|
*/
|
|
|
spin_lock_irq(&uap->port.lock);
|
|
|
- uap->im = UART011_RXIM | UART011_RTIM;
|
|
|
+ uap->im = UART011_RTIM;
|
|
|
+ if (!pl011_dma_rx_running(uap))
|
|
|
+ uap->im |= UART011_RXIM;
|
|
|
writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
spin_unlock_irq(&uap->port.lock);
|
|
|
|
|
@@ -1349,7 +1738,7 @@ static struct uart_driver amba_reg = {
|
|
|
.cons = AMBA_CONSOLE,
|
|
|
};
|
|
|
|
|
|
-static int pl011_probe(struct amba_device *dev, struct amba_id *id)
|
|
|
+static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
|
|
|
{
|
|
|
struct uart_amba_port *uap;
|
|
|
struct vendor_data *vendor = id->data;
|