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@@ -3911,21 +3911,12 @@ init_cpu_err:
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static int
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bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
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{
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- u16 pmcsr;
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-
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- pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
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-
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switch (state) {
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case PCI_D0: {
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u32 val;
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- pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
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- (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
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- PCI_PM_CTRL_PME_STATUS);
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-
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- if (pmcsr & PCI_PM_CTRL_STATE_MASK)
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- /* delay required during transition out of D3hot */
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- msleep(20);
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+ pci_enable_wake(bp->pdev, PCI_D0, false);
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+ pci_set_power_state(bp->pdev, PCI_D0);
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val = BNX2_RD(bp, BNX2_EMAC_MODE);
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val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
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@@ -4018,26 +4009,19 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
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bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
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1, 0);
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- pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
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+ pci_wake_from_d3(bp->pdev, bp->wol);
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if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
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(BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {
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if (bp->wol)
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- pmcsr |= 3;
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- }
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- else {
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- pmcsr |= 3;
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- }
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- if (bp->wol) {
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- pmcsr |= PCI_PM_CTRL_PME_ENABLE;
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+ pci_set_power_state(bp->pdev, PCI_D3hot);
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+ } else {
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+ pci_set_power_state(bp->pdev, PCI_D3hot);
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}
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- pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
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- pmcsr);
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/* No more memory access after this point until
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* device is brought back to D0.
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*/
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- udelay(50);
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break;
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}
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default:
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@@ -7081,6 +7065,9 @@ bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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else {
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bp->wol = 0;
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}
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+
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+ device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
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+
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return 0;
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}
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@@ -8369,6 +8356,11 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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bp->wol = 0;
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}
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+ if (bp->flags & BNX2_FLAG_NO_WOL)
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+ device_set_wakeup_capable(&bp->pdev->dev, false);
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+ else
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+ device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
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+
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if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
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bp->tx_quick_cons_trip_int =
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bp->tx_quick_cons_trip;
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