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@@ -127,9 +127,6 @@ MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
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**************************************************************************
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*/
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-/* DMA address mask */
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-#define FALCON_DMA_MASK DMA_BIT_MASK(46)
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-
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/* TX DMA length mask (13-bit) */
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#define FALCON_TX_DMA_MASK (4096 - 1)
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@@ -3148,7 +3145,7 @@ struct efx_nic_type falcon_a_nic_type = {
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.buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
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.evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
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.evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
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- .max_dma_mask = FALCON_DMA_MASK,
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+ .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
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.tx_dma_mask = FALCON_TX_DMA_MASK,
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.bug5391_mask = 0xf,
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.rx_buffer_padding = 0x24,
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@@ -3169,7 +3166,7 @@ struct efx_nic_type falcon_b_nic_type = {
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.buf_tbl_base = FR_BZ_BUF_FULL_TBL,
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.evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
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.evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
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- .max_dma_mask = FALCON_DMA_MASK,
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+ .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
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.tx_dma_mask = FALCON_TX_DMA_MASK,
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.bug5391_mask = 0,
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.rx_buffer_padding = 0,
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