|
@@ -78,6 +78,24 @@
|
|
|
#define LEVEL_STRIDE (9)
|
|
|
#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
|
|
|
|
|
|
+/*
|
|
|
+ * This bitmap is used to advertise the page sizes our hardware support
|
|
|
+ * to the IOMMU core, which will then use this information to split
|
|
|
+ * physically contiguous memory regions it is mapping into page sizes
|
|
|
+ * that we support.
|
|
|
+ *
|
|
|
+ * Traditionally the IOMMU core just handed us the mappings directly,
|
|
|
+ * after making sure the size is an order of a 4KiB page and that the
|
|
|
+ * mapping has natural alignment.
|
|
|
+ *
|
|
|
+ * To retain this behavior, we currently advertise that we support
|
|
|
+ * all page sizes that are an order of 4KiB.
|
|
|
+ *
|
|
|
+ * If at some point we'd like to utilize the IOMMU core's new behavior,
|
|
|
+ * we could change this to advertise the real page sizes we support.
|
|
|
+ */
|
|
|
+#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
|
|
|
+
|
|
|
static inline int agaw_to_level(int agaw)
|
|
|
{
|
|
|
return agaw + 2;
|
|
@@ -4066,6 +4084,7 @@ static struct iommu_ops intel_iommu_ops = {
|
|
|
.unmap = intel_iommu_unmap,
|
|
|
.iova_to_phys = intel_iommu_iova_to_phys,
|
|
|
.domain_has_cap = intel_iommu_domain_has_cap,
|
|
|
+ .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
|
|
|
};
|
|
|
|
|
|
static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
|