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@@ -5,7 +5,6 @@
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#include "vb_def.h"
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#include "vb_util.h"
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#include "vb_setmode.h"
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-
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static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
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{ 16, 0x45},
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{ 8, 0x35},
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@@ -35,21 +34,12 @@ XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
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unsigned char data, temp;
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if (HwDeviceExtension->jChipType < XG20) {
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- if (*pVBInfo->pSoftSetting & SoftDRAMType) {
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- data = *pVBInfo->pSoftSetting & 0x07;
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- return data;
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- } else {
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- data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
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- if (data == 0)
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- data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
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- 0x02) >> 1;
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- return data;
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- }
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+ data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
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+ if (data == 0)
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+ data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
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+ 0x02) >> 1;
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+ return data;
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} else if (HwDeviceExtension->jChipType == XG27) {
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- if (*pVBInfo->pSoftSetting & SoftDRAMType) {
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- data = *pVBInfo->pSoftSetting & 0x07;
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- return data;
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- }
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temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
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/* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
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if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
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@@ -92,13 +82,11 @@ static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
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xgifb_reg_set(P3c4, 0x16, 0x00);
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xgifb_reg_set(P3c4, 0x16, 0x80);
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- if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
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- mdelay(3);
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- xgifb_reg_set(P3c4, 0x18, 0x00);
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- xgifb_reg_set(P3c4, 0x19, 0x20);
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- xgifb_reg_set(P3c4, 0x16, 0x00);
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- xgifb_reg_set(P3c4, 0x16, 0x80);
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- }
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+ mdelay(3);
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+ xgifb_reg_set(P3c4, 0x18, 0x00);
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+ xgifb_reg_set(P3c4, 0x19, 0x20);
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+ xgifb_reg_set(P3c4, 0x16, 0x00);
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+ xgifb_reg_set(P3c4, 0x16, 0x80);
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udelay(60);
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xgifb_reg_set(P3c4,
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@@ -172,7 +160,7 @@ static void XGINew_DDRII_Bootup_XG27(
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/* Set Double Frequency */
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/* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
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- xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
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+ xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
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udelay(200);
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@@ -532,7 +520,7 @@ static void XGINew_SetDRAMDefaultRegister340(
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pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
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if (HwDeviceExtension->jChipType == XG27)
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- xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
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+ xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
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for (j = 0; j <= 6; j++) /* CR90 - CR96 */
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xgifb_reg_set(P3d4, (0x90 + j),
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@@ -555,7 +543,7 @@ static void XGINew_SetDRAMDefaultRegister340(
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xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
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xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
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- xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
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+ xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
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if (pVBInfo->ram_type) {
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/* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
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xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
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@@ -1075,13 +1063,9 @@ static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
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CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
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if (!(CR3CData & DisplayDeviceFromCMOS)) {
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tempcx = 0x1FF0;
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- if (*pVBInfo->pSoftSetting & ModeSoftSetting)
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- tempbx = 0x1FF0;
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}
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} else {
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tempcx = 0x1FF0;
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- if (*pVBInfo->pSoftSetting & ModeSoftSetting)
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- tempbx = 0x1FF0;
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}
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tempbx &= tempcx;
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@@ -1425,7 +1409,7 @@ unsigned char XGIInitNew(struct pci_dev *pdev)
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printk("10");
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if (HwDeviceExtension->jChipType >= XG20)
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- xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
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+ xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
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/* 3.SetMemoryClock
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@@ -1435,20 +1419,20 @@ unsigned char XGIInitNew(struct pci_dev *pdev)
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printk("11");
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/* 4.SetDefExt1Regs begin */
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- xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
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if (HwDeviceExtension->jChipType == XG27) {
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- xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
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- xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
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}
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xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
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- xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
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/* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
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/* alan, 2001/6/26 Frame buffer can read/write SR20 */
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xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
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/* Hsuan, 2006/01/01 H/W request for slow corner chip */
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xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
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if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
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- xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
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/* SR11 = 0x0F; */
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/* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
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@@ -1534,9 +1518,9 @@ unsigned char XGIInitNew(struct pci_dev *pdev)
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} /* != XG20 */
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/* Set PCI */
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- xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
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- xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
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- xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x25, XGI330_SR25);
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printk("15");
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if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
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@@ -1550,8 +1534,7 @@ unsigned char XGIInitNew(struct pci_dev *pdev)
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temp = (unsigned char) ((temp1 >> 4) & 0x0F);
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xgifb_reg_set(pVBInfo->Part1Port,
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- 0x02,
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- (*pVBInfo->pCRT2Data_1_2));
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+ 0x02, XGI330_CRT2Data_1_2);
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printk("16");
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@@ -1565,15 +1548,15 @@ unsigned char XGIInitNew(struct pci_dev *pdev)
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/* Not DDR */
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xgifb_reg_set(pVBInfo->P3c4,
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0x31,
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- (*pVBInfo->pSR31 & 0x3F) | 0x40);
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+ (XGI330_SR31 & 0x3F) | 0x40);
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xgifb_reg_set(pVBInfo->P3c4,
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0x32,
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- (*pVBInfo->pSR32 & 0xFC) | 0x01);
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+ (XGI330_SR32 & 0xFC) | 0x01);
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} else {
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- xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
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- xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
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}
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- xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
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printk("17");
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/*
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@@ -1584,14 +1567,11 @@ unsigned char XGIInitNew(struct pci_dev *pdev)
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if (pVBInfo->IF_DEF_LVDS == 0) {
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xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
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xgifb_reg_set(pVBInfo->Part4Port,
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- 0x0D,
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- *pVBInfo->pCRT2Data_4_D);
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+ 0x0D, XGI330_CRT2Data_4_D);
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xgifb_reg_set(pVBInfo->Part4Port,
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- 0x0E,
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- *pVBInfo->pCRT2Data_4_E);
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+ 0x0E, XGI330_CRT2Data_4_E);
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xgifb_reg_set(pVBInfo->Part4Port,
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- 0x10,
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- *pVBInfo->pCRT2Data_4_10);
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+ 0x10, XGI330_CRT2Data_4_10);
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xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
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}
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@@ -1651,12 +1631,12 @@ unsigned char XGIInitNew(struct pci_dev *pdev)
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AGP = 0;
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if (AGP == 0)
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- *pVBInfo->pSR21 &= 0xEF;
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+ pVBInfo->SR21 &= 0xEF;
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- xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x21, pVBInfo->SR21);
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if (AGP == 1)
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- *pVBInfo->pSR22 &= 0x20;
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- xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
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+ pVBInfo->SR22 &= 0x20;
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+ xgifb_reg_set(pVBInfo->P3c4, 0x22, pVBInfo->SR22);
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*/
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/* base = 0x80000000; */
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/* OutPortLong(0xcf8, base); */
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@@ -1664,12 +1644,12 @@ unsigned char XGIInitNew(struct pci_dev *pdev)
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/* if (Temp == 0x1039) { */
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xgifb_reg_set(pVBInfo->P3c4,
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0x22,
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- (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
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+ (unsigned char) ((pVBInfo->SR22) & 0xFE));
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/* } else { */
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- /* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
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+ /* xgifb_reg_set(pVBInfo->P3c4, 0x22, pVBInfo->SR22); */
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/* } */
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- xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
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+ xgifb_reg_set(pVBInfo->P3c4, 0x21, pVBInfo->SR21);
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printk("23");
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