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@@ -2666,7 +2666,6 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
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INI_RA(&ah->iniPcieSerdes, i, 1));
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}
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- udelay(1000);
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} else if (AR_SREV_9280(ah) &&
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(ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
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REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
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@@ -2690,7 +2689,6 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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/* Load the new settings */
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REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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- udelay(1000);
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} else {
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REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
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REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
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@@ -2714,6 +2712,8 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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}
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+ udelay(1000);
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+
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/* set bit 19 to allow forcing of pcie core into L1 state */
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REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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