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@@ -2543,6 +2543,7 @@ static void qla4_8xxx_process_fw_error(struct scsi_qla_host *ha)
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void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
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{
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uint32_t dev_state;
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+ uint32_t idc_ctrl;
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/* don't poll if reset is going on */
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if (!(test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
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@@ -2561,10 +2562,23 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
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qla4xxx_wake_dpc(ha);
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} else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
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!test_bit(DPC_RESET_HA, &ha->dpc_flags)) {
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+
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+ ql4_printk(KERN_INFO, ha, "%s: HW State: NEED RESET!\n",
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+ __func__);
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+
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+ if (is_qla8032(ha)) {
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+ idc_ctrl = qla4_83xx_rd_reg(ha,
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+ QLA83XX_IDC_DRV_CTRL);
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+ if (!(idc_ctrl & GRACEFUL_RESET_BIT1)) {
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+ ql4_printk(KERN_INFO, ha, "%s: Graceful reset bit is not set\n",
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+ __func__);
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+ qla4xxx_mailbox_premature_completion(
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+ ha);
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+ }
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+ }
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+
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if (is_qla8032(ha) ||
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(is_qla8022(ha) && !ql4xdontresethba)) {
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- ql4_printk(KERN_INFO, ha, "%s: HW State: "
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- "NEED RESET!\n", __func__);
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set_bit(DPC_RESET_HA, &ha->dpc_flags);
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qla4xxx_wake_dpc(ha);
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}
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