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@@ -35,8 +35,27 @@
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*
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*/
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+#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
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+#define MSM_QGIC_DIST_PHYS 0x02080000
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+#define MSM_QGIC_DIST_SIZE SZ_4K
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+
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+#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
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+#define MSM_QGIC_CPU_PHYS 0x02081000
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+#define MSM_QGIC_CPU_SIZE SZ_4K
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+
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+#define MSM_ACC_BASE IOMEM(0xF0002000)
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+#define MSM_ACC_PHYS 0x02001000
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+#define MSM_ACC_SIZE SZ_4K
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+
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+#define MSM_GCC_BASE IOMEM(0xF0003000)
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+#define MSM_GCC_PHYS 0x02082000
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+#define MSM_GCC_SIZE SZ_4K
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+
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#define MSM_TLMM_BASE IOMEM(0xF0004000)
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#define MSM_TLMM_PHYS 0x00800000
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#define MSM_TLMM_SIZE SZ_16K
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+#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000)
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+#define MSM_SHARED_RAM_SIZE SZ_1M
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+
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#endif
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