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@@ -1880,6 +1880,10 @@ i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
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u32 seqno = intel_ring_get_seqno(ring);
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BUG_ON(ring == NULL);
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+ if (obj->ring != ring && obj->last_write_seqno) {
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+ /* Keep the seqno relative to the current ring */
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+ obj->last_write_seqno = seqno;
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+ }
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obj->ring = ring;
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/* Add a reference if we're newly entering the active list. */
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@@ -2653,7 +2657,6 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
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drm_i915_private_t *dev_priv = dev->dev_private;
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int fence_reg;
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int fence_pitch_shift;
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- uint64_t val;
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if (INTEL_INFO(dev)->gen >= 6) {
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fence_reg = FENCE_REG_SANDYBRIDGE_0;
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@@ -2663,8 +2666,23 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
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fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
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}
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+ fence_reg += reg * 8;
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+
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+ /* To w/a incoherency with non-atomic 64-bit register updates,
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+ * we split the 64-bit update into two 32-bit writes. In order
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+ * for a partial fence not to be evaluated between writes, we
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+ * precede the update with write to turn off the fence register,
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+ * and only enable the fence as the last step.
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+ *
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+ * For extra levels of paranoia, we make sure each step lands
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+ * before applying the next step.
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+ */
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+ I915_WRITE(fence_reg, 0);
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+ POSTING_READ(fence_reg);
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+
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if (obj) {
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u32 size = obj->gtt_space->size;
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+ uint64_t val;
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val = (uint64_t)((obj->gtt_offset + size - 4096) &
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0xfffff000) << 32;
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@@ -2673,12 +2691,16 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
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if (obj->tiling_mode == I915_TILING_Y)
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val |= 1 << I965_FENCE_TILING_Y_SHIFT;
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val |= I965_FENCE_REG_VALID;
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- } else
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- val = 0;
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- fence_reg += reg * 8;
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- I915_WRITE64(fence_reg, val);
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- POSTING_READ(fence_reg);
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+ I915_WRITE(fence_reg + 4, val >> 32);
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+ POSTING_READ(fence_reg + 4);
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+
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+ I915_WRITE(fence_reg + 0, val);
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+ POSTING_READ(fence_reg);
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+ } else {
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+ I915_WRITE(fence_reg + 4, 0);
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+ POSTING_READ(fence_reg + 4);
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+ }
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}
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static void i915_write_fence_reg(struct drm_device *dev, int reg,
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@@ -2796,56 +2818,17 @@ static inline int fence_number(struct drm_i915_private *dev_priv,
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return fence - dev_priv->fence_regs;
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}
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-struct write_fence {
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- struct drm_device *dev;
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- struct drm_i915_gem_object *obj;
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- int fence;
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-};
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-
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-static void i915_gem_write_fence__ipi(void *data)
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-{
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- struct write_fence *args = data;
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-
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- /* Required for SNB+ with LLC */
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- wbinvd();
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-
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- /* Required for VLV */
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- i915_gem_write_fence(args->dev, args->fence, args->obj);
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-}
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-
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static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
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struct drm_i915_fence_reg *fence,
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bool enable)
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{
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struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
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- struct write_fence args = {
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- .dev = obj->base.dev,
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- .fence = fence_number(dev_priv, fence),
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- .obj = enable ? obj : NULL,
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- };
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-
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- /* In order to fully serialize access to the fenced region and
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- * the update to the fence register we need to take extreme
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- * measures on SNB+. In theory, the write to the fence register
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- * flushes all memory transactions before, and coupled with the
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- * mb() placed around the register write we serialise all memory
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- * operations with respect to the changes in the tiler. Yet, on
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- * SNB+ we need to take a step further and emit an explicit wbinvd()
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- * on each processor in order to manually flush all memory
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- * transactions before updating the fence register.
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- *
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- * However, Valleyview complicates matter. There the wbinvd is
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- * insufficient and unlike SNB/IVB requires the serialising
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- * register write. (Note that that register write by itself is
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- * conversely not sufficient for SNB+.) To compromise, we do both.
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- */
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- if (INTEL_INFO(args.dev)->gen >= 6)
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- on_each_cpu(i915_gem_write_fence__ipi, &args, 1);
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- else
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- i915_gem_write_fence(args.dev, args.fence, args.obj);
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+ int reg = fence_number(dev_priv, fence);
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+
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+ i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
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if (enable) {
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- obj->fence_reg = args.fence;
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+ obj->fence_reg = reg;
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fence->obj = obj;
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list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
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} else {
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@@ -4611,7 +4594,7 @@ i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
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list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
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if (obj->pages_pin_count == 0)
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cnt += obj->base.size >> PAGE_SHIFT;
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- list_for_each_entry(obj, &dev_priv->mm.inactive_list, global_list)
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+ list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list)
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if (obj->pin_count == 0 && obj->pages_pin_count == 0)
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cnt += obj->base.size >> PAGE_SHIFT;
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Dave Airlie