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@@ -14,7 +14,6 @@
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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-
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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@@ -25,15 +24,89 @@
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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+#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <asm/irq.h>
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-#include <mach/dma-v1.h>
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+#include <mach/dma.h>
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#include <mach/hardware.h>
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#include "dmaengine.h"
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#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
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+#define IMX_DMA_CHANNELS 16
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+
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+#define DMA_MODE_READ 0
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+#define DMA_MODE_WRITE 1
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+#define DMA_MODE_MASK 1
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+
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+#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
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+#define IMX_DMA_MEMSIZE_32 (0 << 4)
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+#define IMX_DMA_MEMSIZE_8 (1 << 4)
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+#define IMX_DMA_MEMSIZE_16 (2 << 4)
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+#define IMX_DMA_TYPE_LINEAR (0 << 10)
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+#define IMX_DMA_TYPE_2D (1 << 10)
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+#define IMX_DMA_TYPE_FIFO (2 << 10)
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+
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+#define IMX_DMA_ERR_BURST (1 << 0)
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+#define IMX_DMA_ERR_REQUEST (1 << 1)
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+#define IMX_DMA_ERR_TRANSFER (1 << 2)
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+#define IMX_DMA_ERR_BUFFER (1 << 3)
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+#define IMX_DMA_ERR_TIMEOUT (1 << 4)
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+
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+#define DMA_DCR 0x00 /* Control Register */
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+#define DMA_DISR 0x04 /* Interrupt status Register */
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+#define DMA_DIMR 0x08 /* Interrupt mask Register */
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+#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
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+#define DMA_DRTOSR 0x10 /* Request timeout Register */
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+#define DMA_DSESR 0x14 /* Transfer Error Status Register */
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+#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
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+#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
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+#define DMA_WSRA 0x40 /* W-Size Register A */
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+#define DMA_XSRA 0x44 /* X-Size Register A */
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+#define DMA_YSRA 0x48 /* Y-Size Register A */
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+#define DMA_WSRB 0x4c /* W-Size Register B */
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+#define DMA_XSRB 0x50 /* X-Size Register B */
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+#define DMA_YSRB 0x54 /* Y-Size Register B */
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+#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
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+#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
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+#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
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+#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
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+#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
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+#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
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+#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
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+#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
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+#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
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+
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+#define DCR_DRST (1<<1)
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+#define DCR_DEN (1<<0)
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+#define DBTOCR_EN (1<<15)
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+#define DBTOCR_CNT(x) ((x) & 0x7fff)
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+#define CNTR_CNT(x) ((x) & 0xffffff)
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+#define CCR_ACRPT (1<<14)
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+#define CCR_DMOD_LINEAR (0x0 << 12)
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+#define CCR_DMOD_2D (0x1 << 12)
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+#define CCR_DMOD_FIFO (0x2 << 12)
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+#define CCR_DMOD_EOBFIFO (0x3 << 12)
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+#define CCR_SMOD_LINEAR (0x0 << 10)
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+#define CCR_SMOD_2D (0x1 << 10)
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+#define CCR_SMOD_FIFO (0x2 << 10)
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+#define CCR_SMOD_EOBFIFO (0x3 << 10)
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+#define CCR_MDIR_DEC (1<<9)
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+#define CCR_MSEL_B (1<<8)
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+#define CCR_DSIZ_32 (0x0 << 6)
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+#define CCR_DSIZ_8 (0x1 << 6)
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+#define CCR_DSIZ_16 (0x2 << 6)
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+#define CCR_SSIZ_32 (0x0 << 4)
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+#define CCR_SSIZ_8 (0x1 << 4)
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+#define CCR_SSIZ_16 (0x2 << 4)
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+#define CCR_REN (1<<3)
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+#define CCR_RPT (1<<2)
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+#define CCR_FRC (1<<1)
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+#define CCR_CEN (1<<0)
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+#define RTOR_EN (1<<15)
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+#define RTOR_CLK (1<<14)
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+#define RTOR_PSC (1<<13)
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enum imxdma_prep_type {
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IMXDMA_DESC_MEMCPY,
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@@ -42,6 +115,39 @@ enum imxdma_prep_type {
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IMXDMA_DESC_CYCLIC,
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};
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+/*
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+ * struct imxdma_channel_internal - i.MX specific DMA extension
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+ * @name: name specified by DMA client
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+ * @irq_handler: client callback for end of transfer
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+ * @err_handler: client callback for error condition
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+ * @data: clients context data for callbacks
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+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
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+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
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+ * @resbytes: total residual number of bytes to transfer
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+ * (it can be lower or same as sum of SG mapped chunk sizes)
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+ * @sgcount: number of chunks to be read/written
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+ *
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+ * Structure is used for IMX DMA processing. It would be probably good
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+ * @struct dma_struct in the future for external interfacing and use
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+ * @struct imxdma_channel_internal only as extension to it.
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+ */
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+
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+struct imxdma_channel_internal {
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+ void *data;
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+ unsigned int dma_mode;
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+ struct scatterlist *sg;
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+ unsigned int resbytes;
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+
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+ int in_use;
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+
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+ u32 ccr_from_device;
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+ u32 ccr_to_device;
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+
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+ struct timer_list watchdog;
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+
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+ int hw_chaining;
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+};
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+
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struct imxdma_desc {
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struct list_head node;
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struct dma_async_tx_descriptor desc;
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@@ -64,9 +170,9 @@ struct imxdma_desc {
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};
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struct imxdma_channel {
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+ struct imxdma_channel_internal internal;
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struct imxdma_engine *imxdma;
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unsigned int channel;
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- unsigned int imxdma_channel;
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struct tasklet_struct dma_tasklet;
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struct list_head ld_free;
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@@ -84,13 +190,11 @@ struct imxdma_channel {
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struct scatterlist *sg_list;
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};
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-#define MAX_DMA_CHANNELS 8
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-
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struct imxdma_engine {
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struct device *dev;
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struct device_dma_parameters dma_parms;
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struct dma_device dma_device;
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- struct imxdma_channel channel[MAX_DMA_CHANNELS];
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+ struct imxdma_channel channel[IMX_DMA_CHANNELS];
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};
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static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
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@@ -111,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
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return false;
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}
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-static void imxdma_irq_handler(int channel, void *data)
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+/* TODO: put this inside any struct */
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+static void __iomem *imx_dmav1_baseaddr;
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+static struct clk *dma_clk;
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+
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+static void imx_dmav1_writel(unsigned val, unsigned offset)
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+{
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+ __raw_writel(val, imx_dmav1_baseaddr + offset);
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+}
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+
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+static unsigned imx_dmav1_readl(unsigned offset)
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{
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- struct imxdma_channel *imxdmac = data;
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+ return __raw_readl(imx_dmav1_baseaddr + offset);
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+}
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- tasklet_schedule(&imxdmac->dma_tasklet);
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+static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
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+{
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+ if (cpu_is_mx27())
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+ return imxdma->hw_chaining;
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+ else
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+ return 0;
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+}
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+
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+/*
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+ * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
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+ */
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+static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
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+{
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+ struct imxdma_channel_internal *imxdma = &imxdmac->internal;
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+ unsigned long now;
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+
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+ now = min(imxdma->resbytes, sg->length);
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+ if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
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+ imxdma->resbytes -= now;
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+
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+ if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
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+ imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
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+ else
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+ imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
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+
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+ imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
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+
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+ pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
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+ "size 0x%08x\n", imxdmac->channel,
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+ imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
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+ imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
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+ imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
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+
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+ return now;
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+}
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+
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+static int
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+imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
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+ unsigned int dma_length, unsigned int dev_addr,
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+ unsigned int dmamode)
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+{
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+ int channel = imxdmac->channel;
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+
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+ imxdmac->internal.sg = NULL;
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+ imxdmac->internal.dma_mode = dmamode;
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+
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+ if (!dma_address) {
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+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
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+ channel);
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+ return -EINVAL;
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+ }
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+
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+ if (!dma_length) {
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+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
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+ channel);
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+ return -EINVAL;
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+ }
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+
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+ if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
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+ pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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+ "dev_addr=0x%08x for read\n",
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+ channel, __func__, (unsigned int)dma_address,
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+ dma_length, dev_addr);
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+
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+ imx_dmav1_writel(dev_addr, DMA_SAR(channel));
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+ imx_dmav1_writel(dma_address, DMA_DAR(channel));
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+ imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
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+ } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
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+ pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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+ "dev_addr=0x%08x for write\n",
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+ channel, __func__, (unsigned int)dma_address,
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+ dma_length, dev_addr);
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+
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+ imx_dmav1_writel(dma_address, DMA_SAR(channel));
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+ imx_dmav1_writel(dev_addr, DMA_DAR(channel));
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+ imx_dmav1_writel(imxdmac->internal.ccr_to_device,
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+ DMA_CCR(channel));
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+ } else {
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+ printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
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+ channel);
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+ return -EINVAL;
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+ }
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+
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+ imx_dmav1_writel(dma_length, DMA_CNTR(channel));
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+
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+ return 0;
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+}
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+
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+static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
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+{
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+ int channel = imxdmac->channel;
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+ unsigned long flags;
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+
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+ pr_debug("imxdma%d: imx_dma_enable\n", channel);
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+
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+ if (imxdmac->internal.in_use)
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+ return;
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+
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+ local_irq_save(flags);
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+
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+ imx_dmav1_writel(1 << channel, DMA_DISR);
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+ imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
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+ imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
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+ CCR_ACRPT, DMA_CCR(channel));
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+
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+ if ((cpu_is_mx21() || cpu_is_mx27()) &&
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+ imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
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+ imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
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+ if (imxdmac->internal.sg) {
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+ u32 tmp;
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+ imxdma_sg_next(imxdmac, imxdmac->internal.sg);
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+ tmp = imx_dmav1_readl(DMA_CCR(channel));
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+ imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
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+ DMA_CCR(channel));
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+ }
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+ }
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+ imxdmac->internal.in_use = 1;
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+
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+ local_irq_restore(flags);
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+}
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+
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+static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
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+{
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+ int channel = imxdmac->channel;
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+ unsigned long flags;
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+
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+ pr_debug("imxdma%d: imx_dma_disable\n", channel);
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+
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+ if (imxdma_hw_chain(&imxdmac->internal))
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+ del_timer(&imxdmac->internal.watchdog);
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+
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+ local_irq_save(flags);
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+ imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
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+ imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
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+ DMA_CCR(channel));
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+ imx_dmav1_writel(1 << channel, DMA_DISR);
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+ imxdmac->internal.in_use = 0;
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+ local_irq_restore(flags);
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+}
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+
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+static int
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+imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
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+ unsigned int config_mem, unsigned int dmareq, int hw_chaining)
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+{
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+ int channel = imxdmac->channel;
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+ u32 dreq = 0;
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+
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+ imxdmac->internal.hw_chaining = 0;
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+
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+ if (hw_chaining) {
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+ imxdmac->internal.hw_chaining = 1;
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+ if (!imxdma_hw_chain(&imxdmac->internal))
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+ return -EINVAL;
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+ }
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+
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+ if (dmareq)
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+ dreq = CCR_REN;
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+
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+ imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
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+ imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
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+
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+ imx_dmav1_writel(dmareq, DMA_RSSR(channel));
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+
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+ return 0;
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+}
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+
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+static int
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+imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
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+ struct scatterlist *sg, unsigned int sgcount,
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+ unsigned int dma_length, unsigned int dev_addr,
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+ unsigned int dmamode)
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+{
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+ int channel = imxdmac->channel;
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+
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+ if (imxdmac->internal.in_use)
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+ return -EBUSY;
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+
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+ imxdmac->internal.sg = sg;
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+ imxdmac->internal.dma_mode = dmamode;
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+ imxdmac->internal.resbytes = dma_length;
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+
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+ if (!sg || !sgcount) {
|
|
|
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
|
|
|
+ channel);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!sg->length) {
|
|
|
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
|
|
|
+ channel);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
|
|
|
+ pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
|
|
|
+ "dev_addr=0x%08x for read\n",
|
|
|
+ channel, __func__, sg, sgcount, dma_length, dev_addr);
|
|
|
+
|
|
|
+ imx_dmav1_writel(dev_addr, DMA_SAR(channel));
|
|
|
+ imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
|
|
|
+ } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
|
|
|
+ pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
|
|
|
+ "dev_addr=0x%08x for write\n",
|
|
|
+ channel, __func__, sg, sgcount, dma_length, dev_addr);
|
|
|
+
|
|
|
+ imx_dmav1_writel(dev_addr, DMA_DAR(channel));
|
|
|
+ imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
|
|
|
+ } else {
|
|
|
+ printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
|
|
|
+ channel);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ imxdma_sg_next(imxdmac, sg);
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-static void imxdma_err_handler(int channel, void *data, int error)
|
|
|
+static void imxdma_watchdog(unsigned long data)
|
|
|
{
|
|
|
- struct imxdma_channel *imxdmac = data;
|
|
|
+ struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
|
|
|
+ int channel = imxdmac->channel;
|
|
|
|
|
|
+ imx_dmav1_writel(0, DMA_CCR(channel));
|
|
|
+ imxdmac->internal.in_use = 0;
|
|
|
+ imxdmac->internal.sg = NULL;
|
|
|
+
|
|
|
+ /* Tasklet watchdog error handler */
|
|
|
tasklet_schedule(&imxdmac->dma_tasklet);
|
|
|
+ pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
|
|
|
+}
|
|
|
+
|
|
|
+static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
|
|
|
+{
|
|
|
+ struct imxdma_engine *imxdma = dev_id;
|
|
|
+ struct imxdma_channel_internal *internal;
|
|
|
+ unsigned int err_mask;
|
|
|
+ int i, disr;
|
|
|
+ int errcode;
|
|
|
+
|
|
|
+ disr = imx_dmav1_readl(DMA_DISR);
|
|
|
+
|
|
|
+ err_mask = imx_dmav1_readl(DMA_DBTOSR) |
|
|
|
+ imx_dmav1_readl(DMA_DRTOSR) |
|
|
|
+ imx_dmav1_readl(DMA_DSESR) |
|
|
|
+ imx_dmav1_readl(DMA_DBOSR);
|
|
|
+
|
|
|
+ if (!err_mask)
|
|
|
+ return IRQ_HANDLED;
|
|
|
+
|
|
|
+ imx_dmav1_writel(disr & err_mask, DMA_DISR);
|
|
|
+
|
|
|
+ for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
|
+ if (!(err_mask & (1 << i)))
|
|
|
+ continue;
|
|
|
+ internal = &imxdma->channel[i].internal;
|
|
|
+ errcode = 0;
|
|
|
+
|
|
|
+ if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
|
|
|
+ imx_dmav1_writel(1 << i, DMA_DBTOSR);
|
|
|
+ errcode |= IMX_DMA_ERR_BURST;
|
|
|
+ }
|
|
|
+ if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
|
|
|
+ imx_dmav1_writel(1 << i, DMA_DRTOSR);
|
|
|
+ errcode |= IMX_DMA_ERR_REQUEST;
|
|
|
+ }
|
|
|
+ if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
|
|
|
+ imx_dmav1_writel(1 << i, DMA_DSESR);
|
|
|
+ errcode |= IMX_DMA_ERR_TRANSFER;
|
|
|
+ }
|
|
|
+ if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
|
|
|
+ imx_dmav1_writel(1 << i, DMA_DBOSR);
|
|
|
+ errcode |= IMX_DMA_ERR_BUFFER;
|
|
|
+ }
|
|
|
+ /* Tasklet error handler */
|
|
|
+ tasklet_schedule(&imxdma->channel[i].dma_tasklet);
|
|
|
+
|
|
|
+ printk(KERN_WARNING
|
|
|
+ "DMA timeout on channel %d -%s%s%s%s\n", i,
|
|
|
+ errcode & IMX_DMA_ERR_BURST ? " burst" : "",
|
|
|
+ errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
|
|
|
+ errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
|
|
|
+ errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
|
|
|
+ }
|
|
|
+ return IRQ_HANDLED;
|
|
|
}
|
|
|
|
|
|
-static void imxdma_progression(int channel, void *data,
|
|
|
- struct scatterlist *sg)
|
|
|
+static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
|
|
|
{
|
|
|
- struct imxdma_channel *imxdmac = data;
|
|
|
+ struct imxdma_channel_internal *imxdma = &imxdmac->internal;
|
|
|
+ int chno = imxdmac->channel;
|
|
|
+
|
|
|
+ if (imxdma->sg) {
|
|
|
+ u32 tmp;
|
|
|
+ imxdma->sg = sg_next(imxdma->sg);
|
|
|
+
|
|
|
+ if (imxdma->sg) {
|
|
|
+ imxdma_sg_next(imxdmac, imxdma->sg);
|
|
|
+
|
|
|
+ tmp = imx_dmav1_readl(DMA_CCR(chno));
|
|
|
+
|
|
|
+ if (imxdma_hw_chain(imxdma)) {
|
|
|
+ /* FIXME: The timeout should probably be
|
|
|
+ * configurable
|
|
|
+ */
|
|
|
+ mod_timer(&imxdma->watchdog,
|
|
|
+ jiffies + msecs_to_jiffies(500));
|
|
|
+
|
|
|
+ tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
|
|
|
+ imx_dmav1_writel(tmp, DMA_CCR(chno));
|
|
|
+ } else {
|
|
|
+ imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
|
|
|
+ tmp |= CCR_CEN;
|
|
|
+ }
|
|
|
+
|
|
|
+ imx_dmav1_writel(tmp, DMA_CCR(chno));
|
|
|
+
|
|
|
+ if (imxdma_chan_is_doing_cyclic(imxdmac))
|
|
|
+ /* Tasklet progression */
|
|
|
+ tasklet_schedule(&imxdmac->dma_tasklet);
|
|
|
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (imxdma_hw_chain(imxdma)) {
|
|
|
+ del_timer(&imxdma->watchdog);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ imx_dmav1_writel(0, DMA_CCR(chno));
|
|
|
+ imxdma->in_use = 0;
|
|
|
+ /* Tasklet irq */
|
|
|
tasklet_schedule(&imxdmac->dma_tasklet);
|
|
|
}
|
|
|
|
|
|
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
|
|
|
+{
|
|
|
+ struct imxdma_engine *imxdma = dev_id;
|
|
|
+ struct imxdma_channel_internal *internal;
|
|
|
+ int i, disr;
|
|
|
+
|
|
|
+ if (cpu_is_mx21() || cpu_is_mx27())
|
|
|
+ imxdma_err_handler(irq, dev_id);
|
|
|
+
|
|
|
+ disr = imx_dmav1_readl(DMA_DISR);
|
|
|
+
|
|
|
+ pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
|
|
|
+ disr);
|
|
|
+
|
|
|
+ imx_dmav1_writel(disr, DMA_DISR);
|
|
|
+ for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
|
+ if (disr & (1 << i)) {
|
|
|
+ internal = &imxdma->channel[i].internal;
|
|
|
+ dma_irq_handle_channel(&imxdma->channel[i]);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return IRQ_HANDLED;
|
|
|
+}
|
|
|
+
|
|
|
static int imxdma_xfer_desc(struct imxdma_desc *d)
|
|
|
{
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
|
|
|
@@ -141,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
|
|
|
/* Configure and enable */
|
|
|
switch (d->type) {
|
|
|
case IMXDMA_DESC_MEMCPY:
|
|
|
- ret = imx_dma_config_channel(imxdmac->imxdma_channel,
|
|
|
+ ret = imxdma_config_channel_hw(imxdmac,
|
|
|
d->config_port, d->config_mem, 0, 0);
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
- ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
|
|
|
+ ret = imxdma_setup_single_hw(imxdmac, d->src,
|
|
|
d->len, d->dest, d->dmamode);
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
break;
|
|
|
+
|
|
|
+ /* Cyclic transfer is the same as slave_sg with special sg configuration. */
|
|
|
case IMXDMA_DESC_CYCLIC:
|
|
|
- ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
|
|
|
- imxdma_progression);
|
|
|
- if (ret < 0)
|
|
|
- return ret;
|
|
|
- /*
|
|
|
- * We fall through here since cyclic transfer is the same as
|
|
|
- * slave_sg adding a progression handler and a specific sg
|
|
|
- * configuration which is done in 'imxdma_prep_dma_cyclic'.
|
|
|
- */
|
|
|
case IMXDMA_DESC_SLAVE_SG:
|
|
|
if (d->dmamode == DMA_MODE_READ)
|
|
|
- ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
|
|
|
+ ret = imxdma_setup_sg_hw(imxdmac, d->sg,
|
|
|
d->sgcount, d->len, d->src, d->dmamode);
|
|
|
else
|
|
|
- ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
|
|
|
+ ret = imxdma_setup_sg_hw(imxdmac, d->sg,
|
|
|
d->sgcount, d->len, d->dest, d->dmamode);
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
@@ -173,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
|
|
|
default:
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
- imx_dma_enable(imxdmac->imxdma_channel);
|
|
|
+ imxdma_enable_hw(imxdmac);
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
@@ -225,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|
|
|
|
|
switch (cmd) {
|
|
|
case DMA_TERMINATE_ALL:
|
|
|
- imx_dma_disable(imxdmac->imxdma_channel);
|
|
|
+ imxdma_disable_hw(imxdmac);
|
|
|
|
|
|
spin_lock_irqsave(&imxdmac->lock, flags);
|
|
|
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
|
|
|
@@ -255,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|
|
mode = IMX_DMA_MEMSIZE_32;
|
|
|
break;
|
|
|
}
|
|
|
- ret = imx_dma_config_channel(imxdmac->imxdma_channel,
|
|
|
+ ret = imxdma_config_channel_hw(imxdmac,
|
|
|
mode | IMX_DMA_TYPE_FIFO,
|
|
|
IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
|
|
|
imxdmac->dma_request, 1);
|
|
|
|
|
|
if (ret)
|
|
|
return ret;
|
|
|
-
|
|
|
- imx_dma_config_burstlen(imxdmac->imxdma_channel,
|
|
|
- imxdmac->watermark_level * imxdmac->word_size);
|
|
|
+ /* Set burst length */
|
|
|
+ imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
|
|
|
+ DMA_BLR(imxdmac->channel));
|
|
|
|
|
|
return 0;
|
|
|
default:
|
|
|
@@ -333,7 +783,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
|
|
|
|
|
|
spin_lock_irqsave(&imxdmac->lock, flags);
|
|
|
|
|
|
- imx_dma_disable(imxdmac->imxdma_channel);
|
|
|
+ imxdma_disable_hw(imxdmac);
|
|
|
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
|
|
|
list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
|
|
|
|
|
|
@@ -520,10 +970,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
|
|
|
}
|
|
|
|
|
|
static int __init imxdma_probe(struct platform_device *pdev)
|
|
|
-{
|
|
|
+ {
|
|
|
struct imxdma_engine *imxdma;
|
|
|
int ret, i;
|
|
|
|
|
|
+ if (cpu_is_mx1())
|
|
|
+ imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
|
|
|
+ else if (cpu_is_mx21())
|
|
|
+ imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
|
|
|
+ else if (cpu_is_mx27())
|
|
|
+ imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
|
|
|
+ else
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ dma_clk = clk_get(NULL, "dma");
|
|
|
+ if (IS_ERR(dma_clk))
|
|
|
+ return PTR_ERR(dma_clk);
|
|
|
+ clk_enable(dma_clk);
|
|
|
+
|
|
|
+ /* reset DMA module */
|
|
|
+ imx_dmav1_writel(DCR_DRST, DMA_DCR);
|
|
|
+
|
|
|
+ if (cpu_is_mx1()) {
|
|
|
+ ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
|
|
|
+ if (ret) {
|
|
|
+ pr_crit("Can't register IRQ for DMA\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
|
|
|
+ if (ret) {
|
|
|
+ pr_crit("Can't register ERRIRQ for DMA\n");
|
|
|
+ free_irq(MX1_DMA_INT, NULL);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* enable DMA module */
|
|
|
+ imx_dmav1_writel(DCR_DEN, DMA_DCR);
|
|
|
+
|
|
|
+ /* clear all interrupts */
|
|
|
+ imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
|
|
|
+
|
|
|
+ /* disable interrupts */
|
|
|
+ imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
|
|
|
+
|
|
|
imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
|
|
|
if (!imxdma)
|
|
|
return -ENOMEM;
|
|
|
@@ -535,19 +1026,22 @@ static int __init imxdma_probe(struct platform_device *pdev)
|
|
|
dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
|
|
|
|
|
|
/* Initialize channel parameters */
|
|
|
- for (i = 0; i < MAX_DMA_CHANNELS; i++) {
|
|
|
+ for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
|
struct imxdma_channel *imxdmac = &imxdma->channel[i];
|
|
|
-
|
|
|
- imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
|
|
|
- DMA_PRIO_MEDIUM);
|
|
|
- if ((int)imxdmac->channel < 0) {
|
|
|
- ret = -ENODEV;
|
|
|
- goto err_init;
|
|
|
+ memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
|
|
|
+ if (cpu_is_mx21() || cpu_is_mx27()) {
|
|
|
+ ret = request_irq(MX2x_INT_DMACH0 + i,
|
|
|
+ dma_irq_handler, 0, "DMA", imxdma);
|
|
|
+ if (ret) {
|
|
|
+ pr_crit("Can't register IRQ %d for DMA channel %d\n",
|
|
|
+ MX2x_INT_DMACH0 + i, i);
|
|
|
+ goto err_init;
|
|
|
+ }
|
|
|
+ init_timer(&imxdmac->internal.watchdog);
|
|
|
+ imxdmac->internal.watchdog.function = &imxdma_watchdog;
|
|
|
+ imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
|
|
|
}
|
|
|
|
|
|
- imx_dma_setup_handlers(imxdmac->imxdma_channel,
|
|
|
- imxdma_irq_handler, imxdma_err_handler, imxdmac);
|
|
|
-
|
|
|
imxdmac->imxdma = imxdma;
|
|
|
spin_lock_init(&imxdmac->lock);
|
|
|
|
|
|
@@ -593,9 +1087,13 @@ static int __init imxdma_probe(struct platform_device *pdev)
|
|
|
return 0;
|
|
|
|
|
|
err_init:
|
|
|
- while (--i >= 0) {
|
|
|
- struct imxdma_channel *imxdmac = &imxdma->channel[i];
|
|
|
- imx_dma_free(imxdmac->imxdma_channel);
|
|
|
+
|
|
|
+ if (cpu_is_mx21() || cpu_is_mx27()) {
|
|
|
+ while (--i >= 0)
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+ free_irq(MX2x_INT_DMACH0 + i, NULL);
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+ } else if cpu_is_mx1() {
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+ free_irq(MX1_DMA_INT, NULL);
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+ free_irq(MX1_DMA_ERR, NULL);
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}
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kfree(imxdma);
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@@ -609,10 +1107,12 @@ static int __exit imxdma_remove(struct platform_device *pdev)
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dma_async_device_unregister(&imxdma->dma_device);
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- for (i = 0; i < MAX_DMA_CHANNELS; i++) {
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- struct imxdma_channel *imxdmac = &imxdma->channel[i];
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-
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- imx_dma_free(imxdmac->imxdma_channel);
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+ if (cpu_is_mx21() || cpu_is_mx27()) {
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+ for (i = 0; i < IMX_DMA_CHANNELS; i++)
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+ free_irq(MX2x_INT_DMACH0 + i, NULL);
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+ } else if cpu_is_mx1() {
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+ free_irq(MX1_DMA_INT, NULL);
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+ free_irq(MX1_DMA_ERR, NULL);
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}
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kfree(imxdma);
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Javier Martin