|
@@ -1961,7 +1961,13 @@ static int wm8962_readable_register(struct snd_soc_codec *codec, unsigned int re
|
|
|
|
|
|
static int wm8962_reset(struct snd_soc_codec *codec)
|
|
|
{
|
|
|
- return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243);
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ ret = snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243);
|
|
|
+ if (ret != 0)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ return snd_soc_write(codec, WM8962_PLL_SOFTWARE_RESET, 0);
|
|
|
}
|
|
|
|
|
|
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
|
|
@@ -2360,15 +2366,14 @@ static int sysclk_event(struct snd_soc_dapm_widget *w,
|
|
|
|
|
|
snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
|
|
|
WM8962_FLL_ENA, WM8962_FLL_ENA);
|
|
|
- if (wm8962->irq) {
|
|
|
- timeout = msecs_to_jiffies(5);
|
|
|
- timeout = wait_for_completion_timeout(&wm8962->fll_lock,
|
|
|
- timeout);
|
|
|
-
|
|
|
- if (timeout == 0)
|
|
|
- dev_err(codec->dev,
|
|
|
- "Timed out starting FLL\n");
|
|
|
- }
|
|
|
+
|
|
|
+ timeout = msecs_to_jiffies(5);
|
|
|
+ timeout = wait_for_completion_timeout(&wm8962->fll_lock,
|
|
|
+ timeout);
|
|
|
+
|
|
|
+ if (wm8962->irq && timeout == 0)
|
|
|
+ dev_err(codec->dev,
|
|
|
+ "Timed out starting FLL\n");
|
|
|
}
|
|
|
break;
|
|
|
|
|
@@ -4029,6 +4034,11 @@ static int wm8962_probe(struct snd_soc_codec *codec)
|
|
|
snd_soc_update_bits(codec, WM8962_CLOCKING2,
|
|
|
WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
|
|
|
|
|
|
+ /* Ensure that the oscillator and PLLs are disabled */
|
|
|
+ snd_soc_update_bits(codec, WM8962_PLL2,
|
|
|
+ WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
|
|
|
+ 0);
|
|
|
+
|
|
|
regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
|
|
|
|
|
|
if (pdata) {
|