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@@ -927,12 +927,6 @@ asmlinkage void do_reserved(struct pt_regs *regs)
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(regs->cp0_cause & 0x7f) >> 2);
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}
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-static asmlinkage void do_default_vi(void)
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-{
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- show_regs(get_irq_regs());
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- panic("Caught unexpected vectored interrupt.");
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-}
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-
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/*
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* Some MIPS CPUs can enable/disable for cache parity detection, but do
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* it different ways.
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@@ -1128,6 +1122,12 @@ void mips_srs_free(int set)
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clear_bit(set, &sr->sr_allocated);
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}
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+static asmlinkage void do_default_vi(void)
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+{
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+ show_regs(get_irq_regs());
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+ panic("Caught unexpected vectored interrupt.");
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+}
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+
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static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
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{
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unsigned long handler;
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