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@@ -166,6 +166,7 @@ struct nvc0_pm_clock {
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struct nvc0_pm_state {
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struct nouveau_pm_level *perflvl;
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struct nvc0_pm_clock eng[16];
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+ struct nvc0_pm_clock mem;
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};
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static u32
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@@ -304,6 +305,48 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
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return 0;
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}
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+static int
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+calc_mem(struct drm_device *dev, struct nvc0_pm_clock *info, u32 freq)
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+{
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+ struct pll_lims pll;
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+ int N, M, P, ret;
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+ u32 ctrl;
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+
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+ /* mclk pll input freq comes from another pll, make sure it's on */
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+ ctrl = nv_rd32(dev, 0x132020);
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+ if (!(ctrl & 0x00000001)) {
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+ /* if not, program it to 567MHz. nfi where this value comes
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+ * from - it looks like it's in the pll limits table for
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+ * 132000 but the binary driver ignores all my attempts to
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+ * change this value.
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+ */
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+ nv_wr32(dev, 0x137320, 0x00000103);
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+ nv_wr32(dev, 0x137330, 0x81200606);
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+ nv_wait(dev, 0x132020, 0x00010000, 0x00010000);
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+ nv_wr32(dev, 0x132024, 0x0001150f);
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+ nv_mask(dev, 0x132020, 0x00000001, 0x00000001);
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+ nv_wait(dev, 0x137390, 0x00020000, 0x00020000);
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+ nv_mask(dev, 0x132020, 0x00000004, 0x00000004);
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+ }
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+
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+ /* for the moment, until the clock tree is better understood, use
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+ * pll mode for all clock frequencies
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+ */
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+ ret = get_pll_limits(dev, 0x132000, &pll);
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+ if (ret == 0) {
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+ pll.refclk = read_pll(dev, 0x132020);
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+ if (pll.refclk) {
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+ ret = nva3_calc_pll(dev, &pll, freq, &N, NULL, &M, &P);
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+ if (ret > 0) {
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+ info->coef = (P << 16) | (N << 8) | M;
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+ return 0;
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+ }
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+ }
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+ }
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+
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+ return -EINVAL;
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+}
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+
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void *
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nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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@@ -336,6 +379,14 @@ nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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return ERR_PTR(ret);
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}
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+ if (perflvl->memory) {
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+ ret = calc_mem(dev, &info->mem, perflvl->memory);
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+ if (ret) {
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+ kfree(info);
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+ return ERR_PTR(ret);
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+ }
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+ }
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+
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info->perflvl = perflvl;
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return info;
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}
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