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@@ -64,9 +64,28 @@
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#include <asm/apic.h>
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#define __apicdebuginit(type) static type __init
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+
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#define for_each_irq_pin(entry, head) \
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for (entry = head; entry; entry = entry->next)
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+static void __init __ioapic_init_mappings(void);
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+
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+static unsigned int __io_apic_read (unsigned int apic, unsigned int reg);
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+static void __io_apic_write (unsigned int apic, unsigned int reg, unsigned int val);
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+static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
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+
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+static struct io_apic_ops io_apic_ops = {
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+ .init = __ioapic_init_mappings,
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+ .read = __io_apic_read,
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+ .write = __io_apic_write,
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+ .modify = __io_apic_modify,
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+};
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+
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+void __init set_io_apic_ops(const struct io_apic_ops *ops)
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+{
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+ io_apic_ops = *ops;
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+}
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+
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/*
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* Is the SiS APIC rmw bug present ?
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* -1 = don't know, 0 = no, 1 = yes
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@@ -294,6 +313,22 @@ static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
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irq_free_desc(at);
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}
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+static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
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+{
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+ return io_apic_ops.read(apic, reg);
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+}
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+
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+static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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+{
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+ io_apic_ops.write(apic, reg, value);
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+}
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+
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+static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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+{
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+ io_apic_ops.modify(apic, reg, value);
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+}
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+
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+
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struct io_apic {
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unsigned int index;
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unsigned int unused[3];
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@@ -314,16 +349,17 @@ static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
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writel(vector, &io_apic->eoi);
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}
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-static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
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+static unsigned int __io_apic_read(unsigned int apic, unsigned int reg)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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writel(reg, &io_apic->index);
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return readl(&io_apic->data);
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}
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-static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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+static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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+
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writel(reg, &io_apic->index);
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writel(value, &io_apic->data);
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}
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@@ -334,7 +370,7 @@ static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned i
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*
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* Older SiS APIC requires we rewrite the index register
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*/
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-static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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+static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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{
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struct io_apic __iomem *io_apic = io_apic_base(apic);
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@@ -377,6 +413,7 @@ static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
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eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
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eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
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+
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return eu.entry;
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}
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@@ -384,9 +421,11 @@ static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
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{
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union entry_union eu;
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unsigned long flags;
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+
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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eu.entry = __ioapic_read_entry(apic, pin);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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+
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return eu.entry;
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}
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@@ -396,8 +435,7 @@ static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
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* the interrupt, and we need to make sure the entry is fully populated
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* before that happens.
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*/
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-static void
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-__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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+static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
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union entry_union eu = {{0, 0}};
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@@ -409,6 +447,7 @@ __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
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unsigned long flags;
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+
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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__ioapic_write_entry(apic, pin, e);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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@@ -435,8 +474,7 @@ static void ioapic_mask_entry(int apic, int pin)
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* shared ISA-space IRQs, so we have to support them. We are super
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* fast in the common case, and fast for shared ISA-space IRQs.
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*/
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-static int
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-__add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
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+static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
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{
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struct irq_pin_list **last, *entry;
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@@ -521,6 +559,7 @@ static void io_apic_sync(struct irq_pin_list *entry)
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* a dummy read from the IO-APIC
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*/
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struct io_apic __iomem *io_apic;
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+
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io_apic = io_apic_base(entry->apic);
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readl(&io_apic->data);
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}
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@@ -2512,21 +2551,73 @@ static void ack_apic_edge(struct irq_data *data)
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atomic_t irq_mis_count;
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-static void ack_apic_level(struct irq_data *data)
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-{
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- struct irq_cfg *cfg = data->chip_data;
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- int i, do_unmask_irq = 0, irq = data->irq;
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- unsigned long v;
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-
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- irq_complete_move(cfg);
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#ifdef CONFIG_GENERIC_PENDING_IRQ
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+static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
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+{
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/* If we are moving the irq we need to mask it */
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if (unlikely(irqd_is_setaffinity_pending(data))) {
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- do_unmask_irq = 1;
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mask_ioapic(cfg);
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+ return true;
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}
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+ return false;
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+}
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+
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+static inline void ioapic_irqd_unmask(struct irq_data *data,
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+ struct irq_cfg *cfg, bool masked)
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+{
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+ if (unlikely(masked)) {
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+ /* Only migrate the irq if the ack has been received.
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+ *
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+ * On rare occasions the broadcast level triggered ack gets
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+ * delayed going to ioapics, and if we reprogram the
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+ * vector while Remote IRR is still set the irq will never
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+ * fire again.
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+ *
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+ * To prevent this scenario we read the Remote IRR bit
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+ * of the ioapic. This has two effects.
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+ * - On any sane system the read of the ioapic will
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+ * flush writes (and acks) going to the ioapic from
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+ * this cpu.
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+ * - We get to see if the ACK has actually been delivered.
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+ *
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+ * Based on failed experiments of reprogramming the
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+ * ioapic entry from outside of irq context starting
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+ * with masking the ioapic entry and then polling until
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+ * Remote IRR was clear before reprogramming the
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+ * ioapic I don't trust the Remote IRR bit to be
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+ * completey accurate.
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+ *
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+ * However there appears to be no other way to plug
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+ * this race, so if the Remote IRR bit is not
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+ * accurate and is causing problems then it is a hardware bug
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+ * and you can go talk to the chipset vendor about it.
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+ */
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+ if (!io_apic_level_ack_pending(cfg))
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+ irq_move_masked_irq(data);
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+ unmask_ioapic(cfg);
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+ }
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+}
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+#else
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+static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
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+{
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+ return false;
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+}
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+static inline void ioapic_irqd_unmask(struct irq_data *data,
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+ struct irq_cfg *cfg, bool masked)
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+{
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+}
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#endif
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+static void ack_apic_level(struct irq_data *data)
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+{
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+ struct irq_cfg *cfg = data->chip_data;
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+ int i, irq = data->irq;
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+ unsigned long v;
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+ bool masked;
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+
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+ irq_complete_move(cfg);
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+ masked = ioapic_irqd_mask(data, cfg);
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+
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/*
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* It appears there is an erratum which affects at least version 0x11
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* of I/O APIC (that's the 82093AA and cores integrated into various
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@@ -2581,38 +2672,7 @@ static void ack_apic_level(struct irq_data *data)
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eoi_ioapic_irq(irq, cfg);
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}
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- /* Now we can move and renable the irq */
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- if (unlikely(do_unmask_irq)) {
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- /* Only migrate the irq if the ack has been received.
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- *
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- * On rare occasions the broadcast level triggered ack gets
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- * delayed going to ioapics, and if we reprogram the
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- * vector while Remote IRR is still set the irq will never
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- * fire again.
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- *
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- * To prevent this scenario we read the Remote IRR bit
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- * of the ioapic. This has two effects.
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- * - On any sane system the read of the ioapic will
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- * flush writes (and acks) going to the ioapic from
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- * this cpu.
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- * - We get to see if the ACK has actually been delivered.
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- *
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- * Based on failed experiments of reprogramming the
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- * ioapic entry from outside of irq context starting
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- * with masking the ioapic entry and then polling until
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- * Remote IRR was clear before reprogramming the
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- * ioapic I don't trust the Remote IRR bit to be
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- * completey accurate.
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- *
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- * However there appears to be no other way to plug
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- * this race, so if the Remote IRR bit is not
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- * accurate and is causing problems then it is a hardware bug
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- * and you can go talk to the chipset vendor about it.
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- */
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- if (!io_apic_level_ack_pending(cfg))
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- irq_move_masked_irq(data);
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- unmask_ioapic(cfg);
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- }
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+ ioapic_irqd_unmask(data, cfg, masked);
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}
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#ifdef CONFIG_IRQ_REMAP
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@@ -3872,6 +3932,11 @@ static struct resource * __init ioapic_setup_resources(int nr_ioapics)
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}
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void __init ioapic_and_gsi_init(void)
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+{
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+ io_apic_ops.init();
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+}
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+
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+static void __init __ioapic_init_mappings(void)
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{
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unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
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struct resource *ioapic_res;
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