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@@ -488,7 +488,7 @@ enum {
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PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
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PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
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-/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
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+/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
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/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
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/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
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/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
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/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
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/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
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/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
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@@ -511,7 +511,7 @@ enum {
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/*
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/*
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* Bank 4 - 5
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* Bank 4 - 5
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*/
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*/
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-/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
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+/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
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enum {
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enum {
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TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
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TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
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TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
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TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
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@@ -2892,114 +2892,87 @@ static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
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}
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}
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/* MAC Related Registers inside the device. */
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/* MAC Related Registers inside the device. */
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-#define SKGEMAC_REG(port,reg) (((port)<<7)+(reg))
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-
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-/* PCI config space can be accessed via memory mapped space */
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-#define SKGEPCI_REG(reg) ((reg)+ 0x380)
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-
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-#define SKGEXM_REG(port, reg) \
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+#define SK_REG(port,reg) (((port)<<7)+(reg))
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+#define SK_XMAC_REG(port, reg) \
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((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
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((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
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-static inline u32 skge_xm_read32(const struct skge_hw *hw, int port, int reg)
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-{
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- return skge_read32(hw, SKGEXM_REG(port,reg));
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-}
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-
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-static inline u16 skge_xm_read16(const struct skge_hw *hw, int port, int reg)
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-{
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- return skge_read16(hw, SKGEXM_REG(port,reg));
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-}
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-
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-static inline u8 skge_xm_read8(const struct skge_hw *hw, int port, int reg)
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+static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
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{
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{
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- return skge_read8(hw, SKGEXM_REG(port,reg));
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+ u32 v;
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+ v = skge_read16(hw, SK_XMAC_REG(port, reg));
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+ v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
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+ return v;
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}
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}
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-static inline void skge_xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
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+static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
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{
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{
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- skge_write32(hw, SKGEXM_REG(port,r), v);
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+ return skge_read16(hw, SK_XMAC_REG(port,reg));
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}
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}
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-static inline void skge_xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
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+static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
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{
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{
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- skge_write16(hw, SKGEXM_REG(port,r), v);
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+ skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
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+ skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
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}
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}
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-static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8 v)
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+static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
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{
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{
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- skge_write8(hw, SKGEXM_REG(port,r), v);
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+ skge_write16(hw, SK_XMAC_REG(port,r), v);
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}
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}
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-static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg,
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+static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
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const u8 *hash)
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const u8 *hash)
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{
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{
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- skge_xm_write16(hw, port, reg,
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- (u16)hash[0] | ((u16)hash[1] << 8));
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- skge_xm_write16(hw, port, reg+2,
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- (u16)hash[2] | ((u16)hash[3] << 8));
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- skge_xm_write16(hw, port, reg+4,
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- (u16)hash[4] | ((u16)hash[5] << 8));
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- skge_xm_write16(hw, port, reg+6,
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- (u16)hash[6] | ((u16)hash[7] << 8));
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+ xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
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+ xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
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+ xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
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+ xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
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}
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}
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-static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg,
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+static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
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const u8 *addr)
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const u8 *addr)
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{
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{
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- skge_xm_write16(hw, port, reg,
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- (u16)addr[0] | ((u16)addr[1] << 8));
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- skge_xm_write16(hw, port, reg,
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- (u16)addr[2] | ((u16)addr[3] << 8));
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- skge_xm_write16(hw, port, reg,
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- (u16)addr[4] | ((u16)addr[5] << 8));
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+ xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
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+ xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
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+ xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
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}
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}
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+#define SK_GMAC_REG(port,reg) \
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+ (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
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-#define SKGEGMA_REG(port,reg) \
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- ((reg) + BASE_GMAC_1 + \
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- (port) * (BASE_GMAC_2-BASE_GMAC_1))
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-
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-static inline u16 skge_gma_read16(const struct skge_hw *hw, int port, int reg)
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-{
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- return skge_read16(hw, SKGEGMA_REG(port,reg));
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-}
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-
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-static inline u32 skge_gma_read32(const struct skge_hw *hw, int port, int reg)
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+static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
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{
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{
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- return (u32) skge_read16(hw, SKGEGMA_REG(port,reg))
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- | ((u32)skge_read16(hw, SKGEGMA_REG(port,reg+4)) << 16);
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+ return skge_read16(hw, SK_GMAC_REG(port,reg));
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}
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}
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-static inline u8 skge_gma_read8(const struct skge_hw *hw, int port, int reg)
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+static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
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{
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{
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- return skge_read8(hw, SKGEGMA_REG(port,reg));
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+ return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
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+ | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
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}
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}
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-static inline void skge_gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
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+static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
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{
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{
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- skge_write16(hw, SKGEGMA_REG(port,r), v);
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+ skge_write16(hw, SK_GMAC_REG(port,r), v);
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}
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}
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-static inline void skge_gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
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+static inline void gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
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{
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{
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- skge_write16(hw, SKGEGMA_REG(port, r), (u16) v);
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- skge_write32(hw, SKGEGMA_REG(port, r+4), (u16)(v >> 16));
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+ skge_write16(hw, SK_GMAC_REG(port, r), (u16) v);
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+ skge_write32(hw, SK_GMAC_REG(port, r+4), (u16)(v >> 16));
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}
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}
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-static inline void skge_gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
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+static inline void gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
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{
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{
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- skge_write8(hw, SKGEGMA_REG(port,r), v);
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+ skge_write8(hw, SK_GMAC_REG(port,r), v);
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}
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}
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-static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg,
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+static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
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const u8 *addr)
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const u8 *addr)
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{
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{
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- skge_gma_write16(hw, port, reg,
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- (u16) addr[0] | ((u16) addr[1] << 8));
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- skge_gma_write16(hw, port, reg+4,
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- (u16) addr[2] | ((u16) addr[3] << 8));
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- skge_gma_write16(hw, port, reg+8,
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- (u16) addr[4] | ((u16) addr[5] << 8));
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+ gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
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+ gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
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+ gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
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}
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}
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#endif
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#endif
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