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@@ -175,7 +175,6 @@ __v7_setup:
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r10, c2, c0, 2 @ TTB control register
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orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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- mcr p15, 0, r4, c2, c0, 0 @ load TTB0
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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