|
@@ -2821,7 +2821,7 @@ static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
|
|
int i, count = 0;
|
|
int i, count = 0;
|
|
struct MessageUnit_A __iomem *pmuA = acb->pmuA;
|
|
struct MessageUnit_A __iomem *pmuA = acb->pmuA;
|
|
struct MessageUnit_C __iomem *pmuC = acb->pmuC;
|
|
struct MessageUnit_C __iomem *pmuC = acb->pmuC;
|
|
- u32 temp = 0;
|
|
|
|
|
|
+
|
|
/* backup pci config data */
|
|
/* backup pci config data */
|
|
printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
|
|
printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
|
|
for (i = 0; i < 64; i++) {
|
|
for (i = 0; i < 64; i++) {
|
|
@@ -2839,7 +2839,7 @@ static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
|
|
writel(0x2, &pmuC->write_sequence);
|
|
writel(0x2, &pmuC->write_sequence);
|
|
writel(0x7, &pmuC->write_sequence);
|
|
writel(0x7, &pmuC->write_sequence);
|
|
writel(0xD, &pmuC->write_sequence);
|
|
writel(0xD, &pmuC->write_sequence);
|
|
- } while ((((temp = readl(&pmuC->host_diagnostic)) | ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
|
|
|
|
|
|
+ } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
|
|
writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
|
|
writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
|
|
} else {
|
|
} else {
|
|
pci_write_config_byte(acb->pdev, 0x84, 0x20);
|
|
pci_write_config_byte(acb->pdev, 0x84, 0x20);
|