|
@@ -876,21 +876,6 @@ found:
|
|
|
return true;
|
|
|
}
|
|
|
|
|
|
-void intel_dp_init_link_config(struct intel_dp *intel_dp)
|
|
|
-{
|
|
|
- memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
|
|
|
- intel_dp->link_configuration[0] = intel_dp->link_bw;
|
|
|
- intel_dp->link_configuration[1] = intel_dp->lane_count;
|
|
|
- intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
|
|
|
- /*
|
|
|
- * Check for DPCD version > 1.1 and enhanced framing support
|
|
|
- */
|
|
|
- if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
|
|
|
- (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
|
|
|
- intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
|
|
|
{
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
@@ -963,8 +948,6 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
|
|
|
intel_write_eld(&encoder->base, adjusted_mode);
|
|
|
}
|
|
|
|
|
|
- intel_dp_init_link_config(intel_dp);
|
|
|
-
|
|
|
/* Split out the IBX/CPU vs CPT settings */
|
|
|
|
|
|
if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
|
|
@@ -974,7 +957,7 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
|
|
|
intel_dp->DP |= DP_SYNC_VS_HIGH;
|
|
|
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
|
|
|
|
|
|
- if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
|
|
|
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
|
|
intel_dp->DP |= DP_ENHANCED_FRAMING;
|
|
|
|
|
|
intel_dp->DP |= crtc->pipe << 29;
|
|
@@ -988,7 +971,7 @@ static void intel_dp_mode_set(struct intel_encoder *encoder)
|
|
|
intel_dp->DP |= DP_SYNC_VS_HIGH;
|
|
|
intel_dp->DP |= DP_LINK_TRAIN_OFF;
|
|
|
|
|
|
- if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
|
|
|
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
|
|
intel_dp->DP |= DP_ENHANCED_FRAMING;
|
|
|
|
|
|
if (crtc->pipe == 1)
|
|
@@ -2444,14 +2427,21 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
|
|
|
uint8_t voltage;
|
|
|
int voltage_tries, loop_tries;
|
|
|
uint32_t DP = intel_dp->DP;
|
|
|
+ uint8_t link_config[2];
|
|
|
|
|
|
if (HAS_DDI(dev))
|
|
|
intel_ddi_prepare_link_retrain(encoder);
|
|
|
|
|
|
/* Write the link configuration data */
|
|
|
- intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
|
|
|
- intel_dp->link_configuration,
|
|
|
- DP_LINK_CONFIGURATION_SIZE);
|
|
|
+ link_config[0] = intel_dp->link_bw;
|
|
|
+ link_config[1] = intel_dp->lane_count;
|
|
|
+ if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
|
|
+ link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
|
|
+ intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
|
|
|
+
|
|
|
+ link_config[0] = 0;
|
|
|
+ link_config[1] = DP_SET_ANSI_8B10B;
|
|
|
+ intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
|
|
|
|
|
|
DP |= DP_PORT_EN;
|
|
|
|