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@@ -5442,7 +5442,7 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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- u8 port = params->port, initialize = 1;
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+ u8 port, initialize = 1;
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u16 val;
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u16 temp;
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u32 actual_phy_selection;
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@@ -5451,6 +5451,10 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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/* This is just for MDIO_CTL_REG_84823_MEDIA register. */
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msleep(1);
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+ if (CHIP_IS_E2(bp))
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+ port = BP_PATH(bp);
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+ else
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+ port = params->port;
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
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MISC_REGISTERS_GPIO_OUTPUT_HIGH,
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port);
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@@ -5627,7 +5631,11 @@ static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
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struct link_params *params)
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{
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struct bnx2x *bp = params->bp;
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- u8 port = params->port;
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+ u8 port;
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+ if (CHIP_IS_E2(bp))
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+ port = BP_PATH(bp);
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+ else
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+ port = params->port;
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
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MISC_REGISTERS_GPIO_OUTPUT_LOW,
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port);
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@@ -7023,7 +7031,8 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
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return -EINVAL;
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}
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/* disable attentions */
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- bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
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+ bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
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+ port_of_path*4,
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(NIG_MASK_XGXS0_LINK_STATUS |
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NIG_MASK_XGXS0_LINK10G |
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NIG_MASK_SERDES0_LINK_STATUS |
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