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@@ -101,6 +101,8 @@ struct mcp_kreq_ether_recv {
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#define MXGEFW_ETH_SEND_3 0x2c0000
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#define MXGEFW_ETH_RECV_SMALL 0x300000
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#define MXGEFW_ETH_RECV_BIG 0x340000
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+#define MXGEFW_ETH_SEND_GO 0x380000
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+#define MXGEFW_ETH_SEND_STOP 0x3C0000
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#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000))
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#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
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@@ -120,6 +122,11 @@ enum myri10ge_mcp_cmd_type {
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* MXGEFW_CMD_RESET is issued */
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MXGEFW_CMD_SET_INTRQ_DMA,
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+ /* data0 = LSW of the host address
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+ * data1 = MSW of the host address
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+ * data2 = slice number if multiple slices are used
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+ */
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+
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MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */
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MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */
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@@ -129,6 +136,8 @@ enum myri10ge_mcp_cmd_type {
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MXGEFW_CMD_GET_SEND_OFFSET,
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MXGEFW_CMD_GET_SMALL_RX_OFFSET,
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MXGEFW_CMD_GET_BIG_RX_OFFSET,
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+ /* data0 = slice number if multiple slices are used */
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+
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MXGEFW_CMD_GET_IRQ_ACK_OFFSET,
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MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
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@@ -200,7 +209,12 @@ enum myri10ge_mcp_cmd_type {
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MXGEFW_CMD_SET_STATS_DMA_V2,
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/* data0, data1 = bus addr,
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* data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
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- * adding new stuff to mcp_irq_data without changing the ABI */
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+ * adding new stuff to mcp_irq_data without changing the ABI
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+ *
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+ * If multiple slices are used, data2 contains both the size of the
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+ * structure (in the lower 16 bits) and the slice number
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+ * (in the upper 16 bits).
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+ */
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MXGEFW_CMD_UNALIGNED_TEST,
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/* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
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@@ -222,13 +236,18 @@ enum myri10ge_mcp_cmd_type {
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MXGEFW_CMD_GET_MAX_RSS_QUEUES,
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MXGEFW_CMD_ENABLE_RSS_QUEUES,
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/* data0 = number of slices n (0, 1, ..., n-1) to enable
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- * data1 = interrupt mode.
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- * 0=share one INTx/MSI, 1=use one MSI-X per queue.
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+ * data1 = interrupt mode | use of multiple transmit queues.
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+ * 0=share one INTx/MSI.
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+ * 1=use one MSI-X per queue.
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* If all queues share one interrupt, the driver must have set
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* RSS_SHARED_INTERRUPT_DMA before enabling queues.
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+ * 2=enable both receive and send queues.
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+ * Without this bit set, only one send queue (slice 0's send queue)
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+ * is enabled. The receive queues are always enabled.
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*/
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-#define MXGEFW_SLICE_INTR_MODE_SHARED 0
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-#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1
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+#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0
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+#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1
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+#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
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MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET,
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MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA,
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@@ -250,10 +269,13 @@ enum myri10ge_mcp_cmd_type {
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* 2: TCP_IPV4 (required by RSS)
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* 3: IPV4 | TCP_IPV4 (required by RSS)
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* 4: source port
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+ * 5: source port + destination port
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*/
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#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1
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#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2
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#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4
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+#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
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+#define MXGEFW_RSS_HASH_TYPE_MAX 0x5
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MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
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/* Return data = the max. size of the entire headers of a IPv6 TSO packet.
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@@ -329,6 +351,20 @@ enum myri10ge_mcp_cmd_type {
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MXGEFW_CMD_GET_DCA_OFFSET,
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/* offset of dca control for WDMAs */
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+
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+ /* VMWare NetQueue commands */
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+ MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE,
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+ MXGEFW_CMD_NETQ_ADD_FILTER,
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+ /* data0 = filter_id << 16 | queue << 8 | type */
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+ /* data1 = MS4 of MAC Addr */
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+ /* data2 = LS2_MAC << 16 | VLAN_tag */
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+ MXGEFW_CMD_NETQ_DEL_FILTER,
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+ /* data0 = filter_id */
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+ MXGEFW_CMD_NETQ_QUERY1,
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+ MXGEFW_CMD_NETQ_QUERY2,
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+ MXGEFW_CMD_NETQ_QUERY3,
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+ MXGEFW_CMD_NETQ_QUERY4,
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+
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};
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enum myri10ge_mcp_cmd_status {
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@@ -381,4 +417,10 @@ struct mcp_irq_data {
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u8 valid;
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};
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+/* definitions for NETQ filter type */
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+#define MXGEFW_NETQ_FILTERTYPE_NONE 0
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+#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1
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+#define MXGEFW_NETQ_FILTERTYPE_VLAN 2
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+#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3
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+
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#endif /* __MYRI10GE_MCP_H__ */
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