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+#ifndef _ASM_X86_SYSTEM_H_
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+#define _ASM_X86_SYSTEM_H_
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+
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+#include <asm/asm.h>
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+#include <asm/segment.h>
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+#include <asm/cpufeature.h>
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+#include <asm/cmpxchg.h>
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+#include <asm/nops.h>
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+
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+#include <linux/kernel.h>
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+#include <linux/irqflags.h>
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+
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+/* entries in ARCH_DLINFO: */
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+#ifdef CONFIG_IA32_EMULATION
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+# define AT_VECTOR_SIZE_ARCH 2
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+#else
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+# define AT_VECTOR_SIZE_ARCH 1
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+#endif
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+
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+extern unsigned long arch_align_stack(unsigned long sp);
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+
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+void default_idle(void);
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+
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+/*
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+ * Force strict CPU ordering.
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+ * And yes, this is required on UP too when we're talking
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+ * to devices.
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+ */
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+#ifdef CONFIG_X86_32
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+/*
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+ * Some non-Intel clones support out of order store. wmb() ceases to be a
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+ * nop for these.
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+ */
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+#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
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+#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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+#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
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+#else
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+#define mb() asm volatile("mfence":::"memory")
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+#define rmb() asm volatile("lfence":::"memory")
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+#define wmb() asm volatile("sfence" ::: "memory")
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+#endif
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+
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+/**
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+ * read_barrier_depends - Flush all pending reads that subsequents reads
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+ * depend on.
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+ *
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+ * No data-dependent reads from memory-like regions are ever reordered
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+ * over this barrier. All reads preceding this primitive are guaranteed
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+ * to access memory (but not necessarily other CPUs' caches) before any
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+ * reads following this primitive that depend on the data return by
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+ * any of the preceding reads. This primitive is much lighter weight than
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+ * rmb() on most CPUs, and is never heavier weight than is
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+ * rmb().
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+ *
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+ * These ordering constraints are respected by both the local CPU
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+ * and the compiler.
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+ *
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+ * Ordering is not guaranteed by anything other than these primitives,
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+ * not even by data dependencies. See the documentation for
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+ * memory_barrier() for examples and URLs to more information.
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+ *
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+ * For example, the following code would force ordering (the initial
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+ * value of "a" is zero, "b" is one, and "p" is "&a"):
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+ *
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+ * <programlisting>
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+ * CPU 0 CPU 1
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+ *
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+ * b = 2;
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+ * memory_barrier();
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+ * p = &b; q = p;
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+ * read_barrier_depends();
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+ * d = *q;
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+ * </programlisting>
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+ *
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+ * because the read of "*q" depends on the read of "p" and these
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+ * two reads are separated by a read_barrier_depends(). However,
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+ * the following code, with the same initial values for "a" and "b":
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+ *
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+ * <programlisting>
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+ * CPU 0 CPU 1
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+ *
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+ * a = 2;
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+ * memory_barrier();
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+ * b = 3; y = b;
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+ * read_barrier_depends();
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+ * x = a;
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+ * </programlisting>
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+ *
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+ * does not enforce ordering, since there is no data dependency between
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+ * the read of "a" and the read of "b". Therefore, on some CPUs, such
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+ * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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+ * in cases like this where there are no data dependencies.
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+ **/
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+
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+#define read_barrier_depends() do { } while (0)
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+
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+#ifdef CONFIG_SMP
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+#define smp_mb() mb()
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+#ifdef CONFIG_X86_PPRO_FENCE
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+# define smp_rmb() rmb()
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+#else
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+# define smp_rmb() barrier()
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+#endif
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+#ifdef CONFIG_X86_OOSTORE
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+# define smp_wmb() wmb()
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+#else
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+# define smp_wmb() barrier()
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+#endif
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+#define smp_read_barrier_depends() read_barrier_depends()
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+#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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+#else
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+#define smp_mb() barrier()
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+#define smp_rmb() barrier()
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+#define smp_wmb() barrier()
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+#define smp_read_barrier_depends() do { } while (0)
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+#define set_mb(var, value) do { var = value; barrier(); } while (0)
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+#endif
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+
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+/*
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+ * Stop RDTSC speculation. This is needed when you need to use RDTSC
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+ * (or get_cycles or vread that possibly accesses the TSC) in a defined
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+ * code region.
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+ *
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+ * (Could use an alternative three way for this if there was one.)
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+ */
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+static inline void rdtsc_barrier(void)
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+{
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+ alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
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+ alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
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+}
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+
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+#endif
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Al Viro