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@@ -37,16 +37,18 @@
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#define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */
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#define c6_DFAR 16 /* Data Fault Address Register */
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#define c6_IFAR 17 /* Instruction Fault Address Register */
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-#define c9_L2CTLR 18 /* Cortex A15 L2 Control Register */
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-#define c10_PRRR 19 /* Primary Region Remap Register */
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-#define c10_NMRR 20 /* Normal Memory Remap Register */
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-#define c12_VBAR 21 /* Vector Base Address Register */
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-#define c13_CID 22 /* Context ID Register */
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-#define c13_TID_URW 23 /* Thread ID, User R/W */
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-#define c13_TID_URO 24 /* Thread ID, User R/O */
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-#define c13_TID_PRIV 25 /* Thread ID, Privileged */
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-#define c14_CNTKCTL 26 /* Timer Control Register (PL1) */
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-#define NR_CP15_REGS 27 /* Number of regs (incl. invalid) */
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+#define c7_PAR 18 /* Physical Address Register */
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+#define c7_PAR_high 19 /* PAR top 32 bits */
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+#define c9_L2CTLR 20 /* Cortex A15 L2 Control Register */
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+#define c10_PRRR 21 /* Primary Region Remap Register */
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+#define c10_NMRR 22 /* Normal Memory Remap Register */
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+#define c12_VBAR 23 /* Vector Base Address Register */
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+#define c13_CID 24 /* Context ID Register */
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+#define c13_TID_URW 25 /* Thread ID, User R/W */
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+#define c13_TID_URO 26 /* Thread ID, User R/O */
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+#define c13_TID_PRIV 27 /* Thread ID, Privileged */
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+#define c14_CNTKCTL 28 /* Timer Control Register (PL1) */
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+#define NR_CP15_REGS 29 /* Number of regs (incl. invalid) */
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#define ARM_EXCEPTION_RESET 0
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#define ARM_EXCEPTION_UNDEFINED 1
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