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@@ -22,8 +22,8 @@
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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+#include <linux/sh_clk.h>
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#include <asm/clock.h>
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-#include <asm/hwblk.h>
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#include <cpu/sh7722.h>
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/* SH7722 registers */
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@@ -33,6 +33,9 @@
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#define SCLKBCR 0xa415000c
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#define IRDACLKCR 0xa4150018
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#define PLLCR 0xa4150024
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+#define MSTPCR0 0xa4150030
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+#define MSTPCR1 0xa4150034
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+#define MSTPCR2 0xa4150038
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#define DLLFRQ 0xa4150050
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/* Fixed 32 KHz root clock for RTC and Power Management purposes */
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@@ -148,31 +151,31 @@ struct clk div6_clks[DIV6_NR] = {
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};
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static struct clk mstp_clks[HWBLK_NR] = {
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- SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
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- SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
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- SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
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- SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
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- SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
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- SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
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- SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
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- SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
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- SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
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-
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- SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
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- SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
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-
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- SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
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- SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
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- SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
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- SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
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- SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
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- SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
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- SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
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- SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
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- SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
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- SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
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- SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
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- SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
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+ [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
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+ [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
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+ [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
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+ [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
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+ [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
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+ [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
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+ [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
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+ [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
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+ [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
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+
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+ [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
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+ [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
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+
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+ [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
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+ [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
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+ [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
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+ [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
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+ [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
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+ [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
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+ [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
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+ [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
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+ [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
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+ [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
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+ [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
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+ [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
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};
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static struct clk_lookup lookups[] = {
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@@ -205,27 +208,27 @@ static struct clk_lookup lookups[] = {
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CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),
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CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
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- CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
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+ CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
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CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
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- CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
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+ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
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+ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
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+ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
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CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
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CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
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- CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
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- CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
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+ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]),
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+ CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
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CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
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CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
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- CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
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- CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
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+ CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
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+ CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
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CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
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CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
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- CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
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+ CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
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CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
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CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
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- CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
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+ CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
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};
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int __init arch_clk_init(void)
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@@ -258,7 +261,7 @@ int __init arch_clk_init(void)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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if (!ret)
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- ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
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+ ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
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return ret;
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}
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